JPS56106427A - Transister logical circuit - Google Patents

Transister logical circuit

Info

Publication number
JPS56106427A
JPS56106427A JP818380A JP818380A JPS56106427A JP S56106427 A JPS56106427 A JP S56106427A JP 818380 A JP818380 A JP 818380A JP 818380 A JP818380 A JP 818380A JP S56106427 A JPS56106427 A JP S56106427A
Authority
JP
Japan
Prior art keywords
potential
terminal
state
output
ttl
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP818380A
Other languages
Japanese (ja)
Inventor
Masahiro Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP818380A priority Critical patent/JPS56106427A/en
Publication of JPS56106427A publication Critical patent/JPS56106427A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce not only the number of component parts but the power consumption, by using a TTL input circuit and a level converting circuit in common. CONSTITUTION:In case the potential of the input terminal in1 is the maximum level VOL(max) of the ''L'' output potential of the TTL element the 1st state, the base potential VBB of the 1st transistor T5 is decided by the forward potential of the diodes D67 and D8 each. In this instant, the transistor T5 conducts, and the emitter current IS1 flows. Accordingly the voltage of Vout1 VCC-Vbe(T6)- IS1R5 emerges at the output terminal out1. On the other hand, the potential of the terminal in1 is the minimum level VOH(min) of the ''H'' output potential of the TTL element (the 2nd state), the base potential of the T5 is equal to the case of the 1st state. Thus the potential is identical between the T5 and the terminal in1, and accordingly the T5 becomes nonconductive. As a result, the voltage of Vout1 VCC- Vbe(T6) emerges at the terminal out1.
JP818380A 1980-01-25 1980-01-25 Transister logical circuit Pending JPS56106427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP818380A JPS56106427A (en) 1980-01-25 1980-01-25 Transister logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP818380A JPS56106427A (en) 1980-01-25 1980-01-25 Transister logical circuit

Publications (1)

Publication Number Publication Date
JPS56106427A true JPS56106427A (en) 1981-08-24

Family

ID=11686183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP818380A Pending JPS56106427A (en) 1980-01-25 1980-01-25 Transister logical circuit

Country Status (1)

Country Link
JP (1) JPS56106427A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60500987A (en) * 1983-03-30 1985-06-27 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド TTL-ECL input conversion circuit with AND/NAND function
EP0239939A2 (en) * 1986-03-31 1987-10-07 Kabushiki Kaisha Toshiba Input circuit
EP0340720A2 (en) * 1988-05-02 1989-11-08 Kabushiki Kaisha Toshiba Interface circuit
JPH02301220A (en) * 1989-05-15 1990-12-13 Nec Corp Differential logic circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60500987A (en) * 1983-03-30 1985-06-27 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド TTL-ECL input conversion circuit with AND/NAND function
EP0239939A2 (en) * 1986-03-31 1987-10-07 Kabushiki Kaisha Toshiba Input circuit
EP0340720A2 (en) * 1988-05-02 1989-11-08 Kabushiki Kaisha Toshiba Interface circuit
JPH02301220A (en) * 1989-05-15 1990-12-13 Nec Corp Differential logic circuit
JP2546371B2 (en) * 1989-05-15 1996-10-23 日本電気株式会社 Differential logic circuit

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