JPS56117427A - Level converting circuit - Google Patents

Level converting circuit

Info

Publication number
JPS56117427A
JPS56117427A JP2021580A JP2021580A JPS56117427A JP S56117427 A JPS56117427 A JP S56117427A JP 2021580 A JP2021580 A JP 2021580A JP 2021580 A JP2021580 A JP 2021580A JP S56117427 A JPS56117427 A JP S56117427A
Authority
JP
Japan
Prior art keywords
transistor
emitter
level
converting circuit
forms
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021580A
Other languages
Japanese (ja)
Inventor
Masayuki Komon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2021580A priority Critical patent/JPS56117427A/en
Publication of JPS56117427A publication Critical patent/JPS56117427A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01812—Interface arrangements with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the power consumption and realize a high-speed operation, by simplifying the structure of a level converting circuit. CONSTITUTION:The output of the 1st emitter-following EF1 is inputted into the 2nd emitter-follower EF2. The EF2 forms the constant current source to flow the constant current I to the transistor T4. The serial resistances R2 and R3 produce a prescribed difference of potential between the input terminal N2 of the current switch CS and the emitter N3 of the transistor T2, and the diode D1 forming a low- level clamping circuit LDL is connected between the middle connection point N4 and the earth. The collector and the base of the transistor T3 with the emitter earthed via the resistance R4 are connected to the points N1 and N3 respectively to form a high-level clamping circuit HCL. The negative voltage VBB that is intermediate between the L and H of the CML level is applied as the reference voltage to the base of the transistor T6 which forms a pair with the transistor T5 of the input stage among the transistor T5-T8 and resistances R6, R7 that form the current switch CS.
JP2021580A 1980-02-20 1980-02-20 Level converting circuit Pending JPS56117427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021580A JPS56117427A (en) 1980-02-20 1980-02-20 Level converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2021580A JPS56117427A (en) 1980-02-20 1980-02-20 Level converting circuit

Publications (1)

Publication Number Publication Date
JPS56117427A true JPS56117427A (en) 1981-09-14

Family

ID=12020933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021580A Pending JPS56117427A (en) 1980-02-20 1980-02-20 Level converting circuit

Country Status (1)

Country Link
JP (1) JPS56117427A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59103427A (en) * 1982-10-18 1984-06-14 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Signal level converting circuit
US4626706A (en) * 1984-05-24 1986-12-02 Advanced Micro Devices, Inc. Digital signal level translation/master-slave flip flop with look-ahead
JPS62159916A (en) * 1986-01-09 1987-07-15 Toshiba Corp Level conversion circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940663A (en) * 1972-08-23 1974-04-16
JPS5210042A (en) * 1975-07-15 1977-01-26 Nec Corp Level transforming circuit
JPS5347244A (en) * 1976-10-12 1978-04-27 Hitachi Ltd Semiconductor circuit
JPS54128261A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Interface circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4940663A (en) * 1972-08-23 1974-04-16
JPS5210042A (en) * 1975-07-15 1977-01-26 Nec Corp Level transforming circuit
JPS5347244A (en) * 1976-10-12 1978-04-27 Hitachi Ltd Semiconductor circuit
JPS54128261A (en) * 1978-03-29 1979-10-04 Hitachi Ltd Interface circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59103427A (en) * 1982-10-18 1984-06-14 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Signal level converting circuit
JPH0432571B2 (en) * 1982-10-18 1992-05-29
US4626706A (en) * 1984-05-24 1986-12-02 Advanced Micro Devices, Inc. Digital signal level translation/master-slave flip flop with look-ahead
JPS62159916A (en) * 1986-01-09 1987-07-15 Toshiba Corp Level conversion circuit

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