DE3579277D1 - Cmos-ausgangspuffer. - Google Patents

Cmos-ausgangspuffer.

Info

Publication number
DE3579277D1
DE3579277D1 DE8585630149T DE3579277T DE3579277D1 DE 3579277 D1 DE3579277 D1 DE 3579277D1 DE 8585630149 T DE8585630149 T DE 8585630149T DE 3579277 T DE3579277 T DE 3579277T DE 3579277 D1 DE3579277 D1 DE 3579277D1
Authority
DE
Germany
Prior art keywords
output buffer
cmos output
cmos
buffer
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585630149T
Other languages
English (en)
Inventor
Tran Hiep Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE3579277D1 publication Critical patent/DE3579277D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE8585630149T 1984-09-06 1985-09-05 Cmos-ausgangspuffer. Expired - Fee Related DE3579277D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/647,970 US4621208A (en) 1984-09-06 1984-09-06 CMOS output buffer

Publications (1)

Publication Number Publication Date
DE3579277D1 true DE3579277D1 (de) 1990-09-27

Family

ID=24598945

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585630149T Expired - Fee Related DE3579277D1 (de) 1984-09-06 1985-09-05 Cmos-ausgangspuffer.

Country Status (5)

Country Link
US (1) US4621208A (de)
EP (1) EP0174266B1 (de)
JP (1) JPH0616357B2 (de)
KR (1) KR940007001B1 (de)
DE (1) DE3579277D1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621191A (ja) * 1985-03-11 1987-01-07 Nec Ic Microcomput Syst Ltd 信号出力回路
JPS6234830U (de) * 1985-08-19 1987-02-28
US4697107A (en) * 1986-07-24 1987-09-29 National Semiconductor Corporation Four-state I/O control circuit
JPH0786855B2 (ja) * 1987-04-15 1995-09-20 日本電気株式会社 シリアルデ−タ処理装置
US4823029A (en) * 1987-06-25 1989-04-18 American Telephone And Telegraph Company At&T Bell Laboratories Noise controlled output buffer
US4885485A (en) * 1988-08-30 1989-12-05 Vtc Incorporated CMOS Output buffer providing mask programmable output drive current
JP2922028B2 (ja) * 1991-08-30 1999-07-19 株式会社東芝 半導体集積回路の出力回路
US5604453A (en) * 1993-04-23 1997-02-18 Altera Corporation Circuit for reducing ground bounce
US5414312A (en) * 1993-07-15 1995-05-09 Altera Corporation Advanced signal driving buffer with directional input transition detection
KR100532971B1 (ko) * 2004-04-22 2005-12-01 주식회사 하이닉스반도체 메모리 장치용 데이타 출력 장치
US7678000B2 (en) * 2006-06-16 2010-03-16 Cnh America, Llc. Tensioning arrangement for an endless linkage

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5490941A (en) * 1977-12-26 1979-07-19 Hitachi Ltd Driving circuit of tristate type
JPS5570993A (en) * 1978-11-24 1980-05-28 Hitachi Ltd Memory circuit
US4379241A (en) * 1980-05-14 1983-04-05 Motorola, Inc. Edge defined output buffer circuit
US4363978A (en) * 1980-07-31 1982-12-14 Rockwell International Corporation Reduced power tristate driver circuit
JPS57154942A (en) * 1981-03-20 1982-09-24 Hitachi Ltd Cmos tristate circuit
JPS57166733A (en) * 1981-04-06 1982-10-14 Matsushita Electric Ind Co Ltd Electronic circuit
JPS57181231A (en) * 1981-05-01 1982-11-08 Oki Electric Ind Co Ltd Semiconductor integrated circuit
JPS58166830A (ja) * 1982-03-26 1983-10-03 Toshiba Corp 三状態回路
JPS58209225A (ja) * 1982-05-31 1983-12-06 Nec Corp ３ステ−ト出力回路
US4540904A (en) * 1983-05-03 1985-09-10 The United States Of America As Represented By The Secretary Of The Air Force Tri-state type driver circuit

Also Published As

Publication number Publication date
US4621208A (en) 1986-11-04
JPS6165332A (ja) 1986-04-03
KR860002825A (ko) 1986-04-30
JPH0616357B2 (ja) 1994-03-02
EP0174266B1 (de) 1990-08-22
KR940007001B1 (ko) 1994-08-03
EP0174266A3 (en) 1987-10-14
EP0174266A2 (de) 1986-03-12

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: PRINZ, E., DIPL.-ING. LEISER, G., DIPL.-ING. SCHWEPFINGER, K., DIPL.-ING. BUNKE, H., DIPL.-CHEM. DR.RER.NAT. DEGWERT, H., DIPL.-PHYS., PAT.-ANWAELTE, 8000 MUENCHEN

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee