DE3650598D1 - Programmierbare logische Schaltung - Google Patents
Programmierbare logische SchaltungInfo
- Publication number
- DE3650598D1 DE3650598D1 DE3650598T DE3650598T DE3650598D1 DE 3650598 D1 DE3650598 D1 DE 3650598D1 DE 3650598 T DE3650598 T DE 3650598T DE 3650598 T DE3650598 T DE 3650598T DE 3650598 D1 DE3650598 D1 DE 3650598D1
- Authority
- DE
- Germany
- Prior art keywords
- logic circuit
- programmable logic
- programmable
- circuit
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17758—Structural details of configuration resources for speeding up configuration or reconfiguration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17764—Structural details of configuration resources for reliability
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Read Only Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/707,662 US4761768A (en) | 1985-03-04 | 1985-03-04 | Programmable logic device |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3650598D1 true DE3650598D1 (de) | 1997-03-13 |
DE3650598T2 DE3650598T2 (de) | 1997-09-11 |
Family
ID=24842619
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE86301336T Expired - Fee Related DE3688472T2 (de) | 1985-03-04 | 1986-02-25 | Programmierbare logische Schaltung. |
DE3650598T Expired - Fee Related DE3650598T2 (de) | 1985-03-04 | 1986-02-25 | Programmierbare logische Schaltung |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE86301336T Expired - Fee Related DE3688472T2 (de) | 1985-03-04 | 1986-02-25 | Programmierbare logische Schaltung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4761768A (de) |
EP (2) | EP0523817B1 (de) |
JP (2) | JP2607470B2 (de) |
DE (2) | DE3688472T2 (de) |
Families Citing this family (119)
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US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
JPH071493B2 (ja) * | 1987-06-11 | 1995-01-11 | 三菱電機株式会社 | テスト補助回路 |
DE3871889T2 (de) * | 1987-10-02 | 1992-12-24 | Kawasaki Steel Co | Programmierbare eingangs-/ausgangsschaltung. |
US4903223A (en) * | 1988-05-05 | 1990-02-20 | Altera Corporation | Programmable logic device with programmable word line connections |
US4930107A (en) * | 1988-08-08 | 1990-05-29 | Altera Corporation | Method and apparatus for programming and verifying programmable elements in programmable devices |
JP3156966B2 (ja) * | 1988-09-30 | 2001-04-16 | 株式会社東芝 | 不揮発性半導体メモリ装置 |
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-
1985
- 1985-03-04 US US06/707,662 patent/US4761768A/en not_active Expired - Lifetime
-
1986
- 1986-02-25 EP EP92202930A patent/EP0523817B1/de not_active Expired - Lifetime
- 1986-02-25 EP EP86301336A patent/EP0196771B1/de not_active Expired - Lifetime
- 1986-02-25 DE DE86301336T patent/DE3688472T2/de not_active Expired - Fee Related
- 1986-02-25 DE DE3650598T patent/DE3650598T2/de not_active Expired - Fee Related
- 1986-03-04 JP JP4817986A patent/JP2607470B2/ja not_active Expired - Lifetime
-
1994
- 1994-03-28 JP JP8092094A patent/JP2934149B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2934149B2 (ja) | 1999-08-16 |
JPH0774621A (ja) | 1995-03-17 |
EP0196771A3 (en) | 1987-12-16 |
JPS61216520A (ja) | 1986-09-26 |
EP0196771A2 (de) | 1986-10-08 |
US4761768A (en) | 1988-08-02 |
EP0523817A2 (de) | 1993-01-20 |
EP0523817A3 (de) | 1994-03-16 |
EP0196771B1 (de) | 1993-05-26 |
DE3688472D1 (de) | 1993-07-01 |
DE3650598T2 (de) | 1997-09-11 |
JP2607470B2 (ja) | 1997-05-07 |
DE3688472T2 (de) | 1994-01-05 |
EP0523817B1 (de) | 1997-01-29 |
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