DE3639058A1 - Verfahren zur herstellung einer halbleitereinrichtung - Google Patents

Verfahren zur herstellung einer halbleitereinrichtung

Info

Publication number
DE3639058A1
DE3639058A1 DE19863639058 DE3639058A DE3639058A1 DE 3639058 A1 DE3639058 A1 DE 3639058A1 DE 19863639058 DE19863639058 DE 19863639058 DE 3639058 A DE3639058 A DE 3639058A DE 3639058 A1 DE3639058 A1 DE 3639058A1
Authority
DE
Germany
Prior art keywords
region
conductivity type
semiconductor substrate
layer
insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19863639058
Other languages
German (de)
English (en)
Other versions
DE3639058C2 (https=
Inventor
Masayuki Nakajima
Shinichi Sato
Akira Tokui
Akira Kawai
Masao Nagatomo
Hiroji Ozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60284630A external-priority patent/JPS62141759A/ja
Priority claimed from JP60285162A external-priority patent/JPS62144351A/ja
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3639058A1 publication Critical patent/DE3639058A1/de
Application granted granted Critical
Publication of DE3639058C2 publication Critical patent/DE3639058C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/25—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons against alpha rays, e.g. for outer space applications
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE19863639058 1985-12-16 1986-11-14 Verfahren zur herstellung einer halbleitereinrichtung Granted DE3639058A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60284630A JPS62141759A (ja) 1985-12-16 1985-12-16 半導体記憶装置の製造方法
JP60285162A JPS62144351A (ja) 1985-12-18 1985-12-18 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
DE3639058A1 true DE3639058A1 (de) 1987-06-19
DE3639058C2 DE3639058C2 (https=) 1991-06-20

Family

ID=26555550

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863639058 Granted DE3639058A1 (de) 1985-12-16 1986-11-14 Verfahren zur herstellung einer halbleitereinrichtung

Country Status (2)

Country Link
US (1) US4702796A (https=)
DE (1) DE3639058A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877051A (en) * 1997-08-22 1999-03-02 Micron Technology, Inc. Methods of reducing alpha particle inflicted damage to SRAM cells, methods of forming integrated circuitry, and methods of forming SRAM cells
US6979627B2 (en) * 2004-04-30 2005-12-27 Freescale Semiconductor, Inc. Isolation trench
US7670895B2 (en) 2006-04-24 2010-03-02 Freescale Semiconductor, Inc Process of forming an electronic device including a semiconductor layer and another layer adjacent to an opening within the semiconductor layer
US7491622B2 (en) 2006-04-24 2009-02-17 Freescale Semiconductor, Inc. Process of forming an electronic device including a layer formed using an inductively coupled plasma
US7528078B2 (en) 2006-05-12 2009-05-05 Freescale Semiconductor, Inc. Process of forming electronic device including a densified nitride layer adjacent to an opening within a semiconductor layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55160463A (en) * 1979-06-01 1980-12-13 Fujitsu Ltd Semiconductor memory device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4335502A (en) * 1980-10-01 1982-06-22 Standard Microsystems Corporation Method for manufacturing metal-oxide silicon devices
US4536947A (en) * 1983-07-14 1985-08-27 Intel Corporation CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55160463A (en) * 1979-06-01 1980-12-13 Fujitsu Ltd Semiconductor memory device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Techn. Discl. Bull., Bd.21, No.9, 1979, S.3823-3825 *
IBM Techn. Discl. Bull., Bd.27, No.7a, 1984, S.3883-3886 *

Also Published As

Publication number Publication date
DE3639058C2 (https=) 1991-06-20
US4702796A (en) 1987-10-27

Similar Documents

Publication Publication Date Title
DE3033333C2 (https=)
EP0103043B1 (de) CMOS-Speicherzelle mit potentialmässig schwebendem Speichergate
DE3029125C2 (de) Halbleiterspeicher
DE3040757A1 (de) Halbleiterspeichervorrichtung
DE2756855A1 (de) Verfahren zum herstellen einer matrix aus speicherzellen mit hoher speicherkapazitaet
DE3036869A1 (de) Integrierte halbleiterschaltung, schaltungsprogrammiersystem und schaltungsprogrammierverfahren derselben
DE4340419C2 (de) Herstellungsverfahren für eine Halbleitervorrichtung mit einer Isolierschicht, in der ein Kontaktloch gebildet ist
DE2630571B2 (de) Ein-Transistor-Speicherzelle mit in V-MOS-Technik
DE3224287C2 (https=)
DE2901538A1 (de) Speicherschaltung und variabler widerstand zur verwendung in derselben
DE3543937C2 (https=)
EP0027565B1 (de) Dynamische Speicherzelle mit zwei komplementären bipolaren Transistoren
DE3638017C2 (https=)
DE3140268A1 (de) Halbleiteranordnung mit mindestens einem feldeffekttransistor und verfahren zu ihrer herstellung
DE2703871C2 (de) Halbleiterspeicher mit wenigstens einem V-MOS-Transistor
DE3145101C2 (de) Verfahren zur Herstellung eines Halbleiterspeichers
DE4034169C2 (de) DRAM mit einem Speicherzellenfeld und Herstellungsverfahren dafür
DE3639058C2 (https=)
DE2932928A1 (de) Verfahren zur herstellung von vlsi-schaltungen
DE19542240C2 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE4129130A1 (de) Halbleiter-speicherbauelement mit einem gestapelten kondensator
DE68924582T2 (de) Halbleiterspeicher mit erhöhter Zellkapazität auf beschränkter Zellfläche.
DE19756530B4 (de) Verfahren zur Herstellung einer Halbleitereinrichtung
DE4140173A1 (de) Dram und verfahren zu dessen herstellung
DE2657511A1 (de) Monolithisch integrierbare speicherzelle

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee