DE3581914D1 - Halbleiterspeichermatrix mit mehreren verbundenen treibertransistoren. - Google Patents

Halbleiterspeichermatrix mit mehreren verbundenen treibertransistoren.

Info

Publication number
DE3581914D1
DE3581914D1 DE8585116456T DE3581914T DE3581914D1 DE 3581914 D1 DE3581914 D1 DE 3581914D1 DE 8585116456 T DE8585116456 T DE 8585116456T DE 3581914 T DE3581914 T DE 3581914T DE 3581914 D1 DE3581914 D1 DE 3581914D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory matrix
driver transistors
several connected
connected driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585116456T
Other languages
German (de)
English (en)
Inventor
Yukio Takeuchi
Satoshi Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3581914D1 publication Critical patent/DE3581914D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051Deposition of metallic or metal-silicide layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3215Doping the layers
    • H01L21/32155Doping polycristalline - or amorphous silicon layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
DE8585116456T 1984-12-28 1985-12-23 Halbleiterspeichermatrix mit mehreren verbundenen treibertransistoren. Expired - Lifetime DE3581914D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59276181A JPS61156862A (ja) 1984-12-28 1984-12-28 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3581914D1 true DE3581914D1 (de) 1991-04-04

Family

ID=17565841

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585116456T Expired - Lifetime DE3581914D1 (de) 1984-12-28 1985-12-23 Halbleiterspeichermatrix mit mehreren verbundenen treibertransistoren.

Country Status (5)

Country Link
US (2) US4994889A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0186889B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS61156862A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR900008207B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3581914D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5264719A (en) * 1986-01-07 1993-11-23 Harris Corporation High voltage lateral semiconductor device
JPS63136557A (ja) * 1986-11-27 1988-06-08 Matsushita Electronics Corp 記憶装置
US5061654A (en) * 1987-07-01 1991-10-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit having oxide regions with different thickness
JP2810042B2 (ja) * 1987-09-16 1998-10-15 株式会社日立製作所 半導体集積回路装置
KR100212098B1 (ko) 1987-09-19 1999-08-02 가나이 쓰도무 반도체 집적회로 장치 및 그 제조 방법과 반도체 집적 회로 장치의 배선기판 및 그 제조 방법
US5734188A (en) * 1987-09-19 1998-03-31 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JPH01129440A (ja) * 1987-11-14 1989-05-22 Fujitsu Ltd 半導体装置
JP2803729B2 (ja) * 1987-11-16 1998-09-24 株式会社 日立製作所 半導体集積回路装置の製造方法
US5917211A (en) * 1988-09-19 1999-06-29 Hitachi, Ltd. Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same
JPH02122563A (ja) * 1988-10-31 1990-05-10 Nec Corp 半導体装置の製造方法
JPH02144963A (ja) * 1988-11-28 1990-06-04 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPH02163962A (ja) * 1988-12-17 1990-06-25 Nec Corp Mos型メモリ集積回路装置
JP2770416B2 (ja) * 1989-05-22 1998-07-02 日本電気株式会社 半導体記憶装置
JP2673385B2 (ja) * 1989-10-26 1997-11-05 三菱電機株式会社 半導体装置
DE4034169C2 (de) * 1989-10-26 1994-05-19 Mitsubishi Electric Corp DRAM mit einem Speicherzellenfeld und Herstellungsverfahren dafür
US5234853A (en) * 1990-03-05 1993-08-10 Fujitsu Limited Method of producing a high voltage MOS transistor
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
KR930009127B1 (ko) * 1991-02-25 1993-09-23 삼성전자 주식회사 스택형캐패시터를구비하는반도체메모리장치
KR940000510B1 (ko) * 1991-03-20 1994-01-21 삼성전자 주식회사 반도체 메모리장치 및 그 제조방법
US5324680A (en) * 1991-05-22 1994-06-28 Samsung Electronics, Co. Ltd. Semiconductor memory device and the fabrication method thereof
US5395784A (en) * 1993-04-14 1995-03-07 Industrial Technology Research Institute Method of manufacturing low leakage and long retention time DRAM
US5545926A (en) * 1993-10-12 1996-08-13 Kabushiki Kaisha Toshiba Integrated mosfet device with low resistance peripheral diffusion region contacts and low PN-junction failure memory diffusion contacts
KR100219533B1 (ko) * 1997-01-31 1999-09-01 윤종용 임베디드 메모리소자 및 그 제조방법
US6174756B1 (en) * 1997-09-30 2001-01-16 Siemens Aktiengesellschaft Spacers to block deep junction implants and silicide formation in integrated circuits
US5986314A (en) * 1997-10-08 1999-11-16 Texas Instruments Incorporated Depletion mode MOS capacitor with patterned Vt implants
US6066525A (en) * 1998-04-07 2000-05-23 Lsi Logic Corporation Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process
US20030158786A1 (en) * 1999-02-26 2003-08-21 Skyline Software Systems, Inc. Sending three-dimensional images over a network
JP2002280459A (ja) * 2001-03-21 2002-09-27 Kawasaki Microelectronics Kk 集積回路の製造方法
KR100428788B1 (ko) * 2001-12-03 2004-04-28 삼성전자주식회사 반도체 장치의 커패시터 구조체 및 그 형성 방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413401A (en) * 1979-07-23 1983-11-08 National Semiconductor Corporation Method for making a semiconductor capacitor
JPS5826829B2 (ja) * 1979-08-30 1983-06-06 富士通株式会社 ダイナミックメモリセルの製造方法
JPS56164570A (en) * 1980-05-21 1981-12-17 Fujitsu Ltd Semiconductor memory unit
US4364075A (en) * 1980-09-02 1982-12-14 Intel Corporation CMOS Dynamic RAM cell and method of fabrication
US4409259A (en) * 1980-09-02 1983-10-11 Intel Corporation MOS Dynamic RAM cell and method of fabrication
US4441249A (en) * 1982-05-26 1984-04-10 Bell Telephone Laboratories, Incorporated Semiconductor integrated circuit capacitor
JPS59113659A (ja) * 1982-12-20 1984-06-30 Toshiba Corp Mosダイナミツクメモリ
US4536944A (en) * 1982-12-29 1985-08-27 International Business Machines Corporation Method of making ROM/PLA semiconductor device by late stage personalization
JPS59172265A (ja) * 1983-03-22 1984-09-28 Hitachi Ltd 半導体装置とその製造方法
JPS59211277A (ja) * 1983-05-17 1984-11-30 Toshiba Corp 半導体装置
US4466177A (en) * 1983-06-30 1984-08-21 International Business Machines Corporation Storage capacitor optimization for one device FET dynamic RAM cell

Also Published As

Publication number Publication date
JPS61156862A (ja) 1986-07-16
EP0186889B1 (en) 1991-02-27
US4994889A (en) 1991-02-19
KR900008207B1 (ko) 1990-11-05
US5071784A (en) 1991-12-10
KR860005441A (ko) 1986-07-23
EP0186889A2 (en) 1986-07-09
JPH0433142B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1992-06-02
EP0186889A3 (en) 1987-01-28

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