DE3485323D1 - Addierschaltung mit uebertragungskette des vorladungstyps. - Google Patents
Addierschaltung mit uebertragungskette des vorladungstyps.Info
- Publication number
- DE3485323D1 DE3485323D1 DE8484116153T DE3485323T DE3485323D1 DE 3485323 D1 DE3485323 D1 DE 3485323D1 DE 8484116153 T DE8484116153 T DE 8484116153T DE 3485323 T DE3485323 T DE 3485323T DE 3485323 D1 DE3485323 D1 DE 3485323D1
- Authority
- DE
- Germany
- Prior art keywords
- additional circuit
- transfer chain
- charge type
- charge
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3872—Precharge of output to prevent leakage
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58248517A JPS60134932A (ja) | 1983-12-24 | 1983-12-24 | プリチヤ−ジ型の桁上げ連鎖加算回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3485323D1 true DE3485323D1 (de) | 1992-01-16 |
Family
ID=17179360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484116153T Expired - Lifetime DE3485323D1 (de) | 1983-12-24 | 1984-12-21 | Addierschaltung mit uebertragungskette des vorladungstyps. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4860242A (de) |
EP (1) | EP0147836B1 (de) |
JP (1) | JPS60134932A (de) |
DE (1) | DE3485323D1 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62111325A (ja) * | 1985-07-12 | 1987-05-22 | Mitsubishi Electric Corp | マンチェスタ型キャリィ伝搬回路 |
US4764887A (en) * | 1985-08-02 | 1988-08-16 | Advanced Micro Devices, Inc. | Carry-bypass arithmetic logic unit |
FR2596544B1 (fr) * | 1986-03-28 | 1988-05-13 | Radiotechnique Compelec | Circuit arithmetique et logique |
JPS6382515A (ja) * | 1986-09-27 | 1988-04-13 | Toshiba Corp | 加算器 |
JPS63145526A (ja) * | 1986-12-09 | 1988-06-17 | Mitsubishi Electric Corp | 桁上げ信号伝播回路 |
JPS63240624A (ja) * | 1987-03-28 | 1988-10-06 | Toshiba Corp | 加算器 |
JPS6419432A (en) * | 1987-07-15 | 1989-01-23 | Fujitsu Ltd | Predictive carrying circuit |
JP2992588B2 (ja) * | 1989-06-30 | 1999-12-20 | 三菱電機株式会社 | 加算回路 |
JP3487783B2 (ja) * | 1999-03-17 | 2004-01-19 | 富士通株式会社 | 加算回路、それを利用した積分回路、及びそれを利用した同期確立回路 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3636334A (en) * | 1969-01-02 | 1972-01-18 | Univ California | Parallel adder with distributed control to add a plurality of binary numbers |
US3603766A (en) * | 1969-09-15 | 1971-09-07 | Matsushita Electric Ind Co Ltd | Arc-image zone-refining furnace |
DE2007353C3 (de) * | 1970-02-18 | 1973-11-29 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Vierteiliges Addierwerk |
US3675001A (en) * | 1970-12-10 | 1972-07-04 | Ibm | Fast adder for multi-number additions |
US3723715A (en) * | 1971-08-25 | 1973-03-27 | Ibm | Fast modulo threshold operator binary adder for multi-number additions |
US3767906A (en) * | 1972-01-21 | 1973-10-23 | Rca Corp | Multifunction full adder |
US3728532A (en) * | 1972-01-21 | 1973-04-17 | Rca Corp | Carry skip-ahead network |
US3843876A (en) * | 1973-09-20 | 1974-10-22 | Motorola Inc | Electronic digital adder having a high speed carry propagation line |
US4052604A (en) * | 1976-01-19 | 1977-10-04 | Hewlett-Packard Company | Binary adder |
US4152775A (en) * | 1977-07-20 | 1979-05-01 | Intel Corporation | Single line propagation adder and method for binary addition |
US4399517A (en) * | 1981-03-19 | 1983-08-16 | Texas Instruments Incorporated | Multiple-input binary adder |
US4417314A (en) * | 1981-07-14 | 1983-11-22 | Rockwell International Corporation | Parallel operating mode arithmetic logic unit apparatus |
US4425623A (en) * | 1981-07-14 | 1984-01-10 | Rockwell International Corporation | Lookahead carry circuit apparatus |
US4471454A (en) * | 1981-10-27 | 1984-09-11 | Ibm Corporation | Fast, efficient, small adder |
JPS5892036A (ja) * | 1981-11-27 | 1983-06-01 | Toshiba Corp | 加算回路 |
JPS5896347A (ja) * | 1981-12-03 | 1983-06-08 | Toshiba Corp | 全加算器 |
US4541067A (en) * | 1982-05-10 | 1985-09-10 | American Microsystems, Inc. | Combinational logic structure using PASS transistors |
JPS58211252A (ja) * | 1982-06-03 | 1983-12-08 | Toshiba Corp | 全加算器 |
US4523292A (en) * | 1982-09-30 | 1985-06-11 | Rca Corporation | Complementary FET ripple carry binary adder circuit |
US4536855A (en) * | 1982-12-23 | 1985-08-20 | International Telephone And Telegraph Corporation | Impedance restoration for fast carry propagation |
JPS59139447A (ja) * | 1983-01-28 | 1984-08-10 | Matsushita Electric Ind Co Ltd | 全加算器 |
DE3373566D1 (en) * | 1983-04-15 | 1987-10-15 | Itt Ind Gmbh Deutsche | Cmos - full binary adder |
US4604723A (en) * | 1983-10-17 | 1986-08-05 | Sanders Associates, Inc. | Bit-slice adder circuit |
US4563751A (en) * | 1984-04-26 | 1986-01-07 | Motorola, Inc. | Carry propagate adder circuit which differentially senses a carry input |
-
1983
- 1983-12-24 JP JP58248517A patent/JPS60134932A/ja active Pending
-
1984
- 1984-12-21 EP EP84116153A patent/EP0147836B1/de not_active Expired
- 1984-12-21 DE DE8484116153T patent/DE3485323D1/de not_active Expired - Lifetime
-
1989
- 1989-01-05 US US07/294,940 patent/US4860242A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0147836A3 (en) | 1988-06-01 |
EP0147836B1 (de) | 1991-12-04 |
JPS60134932A (ja) | 1985-07-18 |
EP0147836A2 (de) | 1985-07-10 |
US4860242A (en) | 1989-08-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |