JPS6419432A - Predictive carrying circuit - Google Patents

Predictive carrying circuit

Info

Publication number
JPS6419432A
JPS6419432A JP17487287A JP17487287A JPS6419432A JP S6419432 A JPS6419432 A JP S6419432A JP 17487287 A JP17487287 A JP 17487287A JP 17487287 A JP17487287 A JP 17487287A JP S6419432 A JPS6419432 A JP S6419432A
Authority
JP
Japan
Prior art keywords
carrying
predictive
circuit
bit
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17487287A
Other languages
Japanese (ja)
Inventor
Takashi Ishii
Atsushi Sakurai
Taizo Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17487287A priority Critical patent/JPS6419432A/en
Publication of JPS6419432A publication Critical patent/JPS6419432A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable the predictive carrying of a prescribed number of bits and predictive carrying of its integer multiple length, superposed by the prescribed number of bits, without extending the circuit scale so much by providing a second specific predictive carrying circuit which carries an integer-multiple length of carry of a first unit predictive carrying circuit. CONSTITUTION:The first unit predictive carrying circuit consists of four bits. When carrying occurs throughout four-bit full adders AD4-AD7 and carrying occurs even in the predictive carrying circuit for low-order four-bit full adders AD0-AD3, AND between potentials of lines l6 and l52 inputted to transistors T13 and T14 is operated to constitute the second predictive carrying circuit, and its output is used as the output of 8-bit predictive carrying. The similar circuit is repeatedly constituted at every four-bit full adder group to enable four-bit predictive carrying and eight-bit predictive carrying superposed by every four-bit with each other and it is unnecessary to extend the circuit scale so much.
JP17487287A 1987-07-15 1987-07-15 Predictive carrying circuit Pending JPS6419432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17487287A JPS6419432A (en) 1987-07-15 1987-07-15 Predictive carrying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17487287A JPS6419432A (en) 1987-07-15 1987-07-15 Predictive carrying circuit

Publications (1)

Publication Number Publication Date
JPS6419432A true JPS6419432A (en) 1989-01-23

Family

ID=15986133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17487287A Pending JPS6419432A (en) 1987-07-15 1987-07-15 Predictive carrying circuit

Country Status (1)

Country Link
JP (1) JPS6419432A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134932A (en) * 1983-12-24 1985-07-18 Toshiba Corp Carry chaining addition circuit of precharge type
JPS62144241A (en) * 1985-12-18 1987-06-27 Mitsubishi Electric Corp Adding circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134932A (en) * 1983-12-24 1985-07-18 Toshiba Corp Carry chaining addition circuit of precharge type
JPS62144241A (en) * 1985-12-18 1987-06-27 Mitsubishi Electric Corp Adding circuit

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