DE3477530D1 - Method of forming a metallic silicide - Google Patents

Method of forming a metallic silicide

Info

Publication number
DE3477530D1
DE3477530D1 DE8484104198T DE3477530T DE3477530D1 DE 3477530 D1 DE3477530 D1 DE 3477530D1 DE 8484104198 T DE8484104198 T DE 8484104198T DE 3477530 T DE3477530 T DE 3477530T DE 3477530 D1 DE3477530 D1 DE 3477530D1
Authority
DE
Germany
Prior art keywords
forming
metallic silicide
silicide
metallic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484104198T
Other languages
English (en)
Inventor
Chi Kwan Lau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23954815&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3477530(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE3477530D1 publication Critical patent/DE3477530D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28537—Deposition of Schottky electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
DE8484104198T 1983-05-06 1984-04-13 Method of forming a metallic silicide Expired DE3477530D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/492,069 US4545116A (en) 1983-05-06 1983-05-06 Method of forming a titanium disilicide

Publications (1)

Publication Number Publication Date
DE3477530D1 true DE3477530D1 (en) 1989-05-03

Family

ID=23954815

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484104198T Expired DE3477530D1 (en) 1983-05-06 1984-04-13 Method of forming a metallic silicide

Country Status (4)

Country Link
US (1) US4545116A (de)
EP (1) EP0128304B1 (de)
JP (2) JPS6052044A (de)
DE (1) DE3477530D1 (de)

Families Citing this family (50)

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JPS59125640A (ja) * 1982-12-28 1984-07-20 Fujitsu Ltd 半導体装置の製造方法
JPS60217657A (ja) * 1984-04-12 1985-10-31 Mitsubishi Electric Corp 半導体集積回路装置の製造方法
US4829363A (en) * 1984-04-13 1989-05-09 Fairchild Camera And Instrument Corp. Structure for inhibiting dopant out-diffusion
GB2164491B (en) * 1984-09-14 1988-04-07 Stc Plc Semiconductor devices
JPS61137367A (ja) * 1984-12-10 1986-06-25 Hitachi Ltd 半導体集積回路装置の製造方法
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
JPS61214427A (ja) * 1985-03-19 1986-09-24 Nippon Gakki Seizo Kk 半導体装置の電極形成法
US4804636A (en) * 1985-05-01 1989-02-14 Texas Instruments Incorporated Process for making integrated circuits having titanium nitride triple interconnect
US4821085A (en) * 1985-05-01 1989-04-11 Texas Instruments Incorporated VLSI local interconnect structure
US4751198A (en) * 1985-09-11 1988-06-14 Texas Instruments Incorporated Process for making contacts and interconnections using direct-reacted silicide
JP2615390B2 (ja) * 1985-10-07 1997-05-28 工業技術院長 炭化シリコン電界効果トランジスタの製造方法
JPH0682641B2 (ja) * 1985-10-21 1994-10-19 日本電気株式会社 半導体集積回路装置の製造方法
US4663191A (en) * 1985-10-25 1987-05-05 International Business Machines Corporation Salicide process for forming low sheet resistance doped silicon junctions
US4746219A (en) * 1986-03-07 1988-05-24 Texas Instruments Incorporated Local interconnect
US4983544A (en) * 1986-10-20 1991-01-08 International Business Machines Corporation Silicide bridge contact process
DE3751773T2 (de) * 1986-12-11 1996-11-28 Fairchild Semiconductor Modifiziertes isoplanares verfahren mit erhöhter dichte
US4849344A (en) * 1986-12-11 1989-07-18 Fairchild Semiconductor Corporation Enhanced density modified isoplanar process
US4855798A (en) * 1986-12-19 1989-08-08 Texas Instruments Incorporated Semiconductor and process of fabrication thereof
US5059546A (en) * 1987-05-01 1991-10-22 Texas Instruments Incorporated BICMOS process for forming shallow NPN emitters and mosfet source/drains
US4816423A (en) * 1987-05-01 1989-03-28 Texas Instruments Incorporated Bicmos process for forming shallow npn emitters and mosfet source/drains
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
FR2624304B1 (fr) * 1987-12-04 1990-05-04 Philips Nv Procede pour etablir une structure d'interconnexion electrique sur un dispositif semiconducteur au silicium
US4873205A (en) * 1987-12-21 1989-10-10 International Business Machines Corporation Method for providing silicide bridge contact between silicon regions separated by a thin dielectric
JPH01173714A (ja) * 1987-12-21 1989-07-10 Internatl Business Mach Corp <Ibm> ブリツジ接点の形成方法
WO1989011732A1 (en) * 1988-05-24 1989-11-30 Micron Technology, Inc. Tisi2 local interconnects
KR930004295B1 (ko) * 1988-12-24 1993-05-22 삼성전자 주식회사 Vlsi 장치의 n+ 및 p+ 저항영역에 저저항 접속방법
US4920073A (en) * 1989-05-11 1990-04-24 Texas Instruments, Incorporated Selective silicidation process using a titanium nitride protective layer
US5059554A (en) * 1989-06-23 1991-10-22 Sgs-Thomson Microelectronics, Inc. Method for forming polycrystalline silicon contacts
US5443996A (en) * 1990-05-14 1995-08-22 At&T Global Information Solutions Company Process for forming titanium silicide local interconnect
US5086017A (en) * 1991-03-21 1992-02-04 Industrial Technology Research Institute Self aligned silicide process for gate/runner without extra masking
US5250834A (en) * 1991-09-19 1993-10-05 International Business Machines Corporation Silicide interconnection with schottky barrier diode isolation
US5387548A (en) * 1992-06-22 1995-02-07 Motorola, Inc. Method of forming an etched ohmic contact
US5344793A (en) * 1993-03-05 1994-09-06 Siemens Aktiengesellschaft Formation of silicided junctions in deep sub-micron MOSFETs by defect enhanced CoSi2 formation
JP3256048B2 (ja) * 1993-09-20 2002-02-12 富士通株式会社 半導体装置及びその製造方法
KR0162673B1 (ko) * 1994-01-11 1998-12-01 문정환 반도체 도전층 및 반도체소자의 제조방법
JP3238820B2 (ja) * 1994-02-18 2001-12-17 富士通株式会社 半導体装置
JPH07263544A (ja) * 1994-03-17 1995-10-13 Fujitsu Ltd 半導体装置及びその製造方法
US5624869A (en) * 1994-04-13 1997-04-29 International Business Machines Corporation Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen
JP2630292B2 (ja) * 1995-02-27 1997-07-16 日本電気株式会社 半導体装置の製造方法
JP2751859B2 (ja) * 1995-03-15 1998-05-18 日本電気株式会社 半導体装置の製造方法
US5654570A (en) * 1995-04-19 1997-08-05 International Business Machines Corporation CMOS gate stack
US6096638A (en) 1995-10-28 2000-08-01 Nec Corporation Method for forming a refractory metal silicide layer
US5733816A (en) * 1995-12-13 1998-03-31 Micron Technology, Inc. Method for depositing a tungsten layer on silicon
GB2320130B (en) * 1996-08-09 2001-11-07 United Microelectronics Corp Improved self-ligned silicide manufacturing method
JPH10189483A (ja) * 1996-12-26 1998-07-21 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
TW326551B (en) * 1997-07-11 1998-02-11 Holtek Microelectronics Inc The manufacturing method for Ti-salicide in IC
US6127276A (en) * 1998-06-02 2000-10-03 United Microelectronics Corp Method of formation for a via opening
US6235630B1 (en) * 1998-08-19 2001-05-22 Micron Technology, Inc. Silicide pattern structures and methods of fabricating the same
DE50112534D1 (de) * 2001-01-04 2007-07-05 Infineon Technologies Ag Verfahren zur kontaktierung eines dotiergebiets eines halbleiterbauelements
JP6823533B2 (ja) * 2017-04-24 2021-02-03 東京エレクトロン株式会社 チタンシリサイド領域を形成する方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3855612A (en) * 1972-01-03 1974-12-17 Signetics Corp Schottky barrier diode semiconductor structure and method
NL7510903A (nl) * 1975-09-17 1977-03-21 Philips Nv Werkwijze voor het vervaardigen van een halfgelei- derinrichting, en inrichting vervaardigd volgens de werkwijze.
US4056642A (en) * 1976-05-14 1977-11-01 Data General Corporation Method of fabricating metal-semiconductor interfaces
US4243865A (en) * 1976-05-14 1981-01-06 Data General Corporation Process for treating material in plasma environment
JPS5333077A (en) * 1976-09-08 1978-03-28 Nec Corp Semiconductor integrated circuit
JPS6057227B2 (ja) * 1976-11-11 1985-12-13 日本電気株式会社 半導体装置の製造方法
JPS5583229A (en) * 1978-12-19 1980-06-23 Fujitsu Ltd Producing semiconductor device
JPS55143051A (en) * 1979-04-26 1980-11-08 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS5671976A (en) * 1979-11-19 1981-06-15 Seiko Epson Corp Preparation method of mos type semiconductor system
JPS584924A (ja) * 1981-07-01 1983-01-12 Hitachi Ltd 半導体装置の電極形成方法

Also Published As

Publication number Publication date
JPH0581664B2 (de) 1993-11-15
EP0128304A1 (de) 1984-12-19
JPS6052044A (ja) 1985-03-23
JPH0365658B2 (de) 1991-10-14
JPH01252763A (ja) 1989-10-09
US4545116A (en) 1985-10-08
EP0128304B1 (de) 1989-03-29

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8365 Fully valid after opposition proceedings