DE3335189A1 - Verfahren zum herstellen einer heterostruktur - Google Patents

Verfahren zum herstellen einer heterostruktur

Info

Publication number
DE3335189A1
DE3335189A1 DE19833335189 DE3335189A DE3335189A1 DE 3335189 A1 DE3335189 A1 DE 3335189A1 DE 19833335189 DE19833335189 DE 19833335189 DE 3335189 A DE3335189 A DE 3335189A DE 3335189 A1 DE3335189 A1 DE 3335189A1
Authority
DE
Germany
Prior art keywords
substrate
stencil
growth
epitaxial
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19833335189
Other languages
German (de)
English (en)
Inventor
John Murray 07043 Upper Montclair N.J. Gibson
John Milo 07901 Summit N.J. Poate
Raymond Tzutse 07922 Berkeley Heights N.J. Tung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE3335189A1 publication Critical patent/DE3335189A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3241—Materials thereof being conductive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
DE19833335189 1982-09-30 1983-09-28 Verfahren zum herstellen einer heterostruktur Withdrawn DE3335189A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/429,291 US4477308A (en) 1982-09-30 1982-09-30 Heteroepitaxy of multiconstituent material by means of a _template layer

Publications (1)

Publication Number Publication Date
DE3335189A1 true DE3335189A1 (de) 1984-04-05

Family

ID=23702624

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19833335189 Withdrawn DE3335189A1 (de) 1982-09-30 1983-09-28 Verfahren zum herstellen einer heterostruktur

Country Status (8)

Country Link
US (1) US4477308A (enExample)
JP (1) JPS5983997A (enExample)
CA (1) CA1209452A (enExample)
DE (1) DE3335189A1 (enExample)
FR (1) FR2534068A1 (enExample)
GB (1) GB2129019B (enExample)
HK (1) HK80886A (enExample)
NL (1) NL8303341A (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4555301A (en) * 1983-06-20 1985-11-26 At&T Bell Laboratories Formation of heterostructures by pulsed melting of precursor material
US4707197A (en) * 1984-08-02 1987-11-17 American Telephone And Telegraph Company, At&T Bell Laboratories Method of producing a silicide/Si heteroepitaxial structure, and articles produced by the method
US4548658A (en) * 1985-01-30 1985-10-22 Cook Melvin S Growth of lattice-graded epilayers
US5047111A (en) * 1985-03-16 1991-09-10 Director-General Of The Agency Of Industrial Science And Technology Method of forming a metal silicide film
GB2183090B (en) * 1985-10-07 1989-09-13 Canon Kk Method for selective formation of deposited film
US5310696A (en) * 1989-06-16 1994-05-10 Massachusetts Institute Of Technology Chemical method for the modification of a substrate surface to accomplish heteroepitaxial crystal growth
US5290715A (en) * 1991-12-31 1994-03-01 U.S. Philips Corporation Method of making dielectrically isolated metal base transistors and permeable base transistors
JP4056571B2 (ja) * 1995-08-02 2008-03-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5728625A (en) * 1996-04-04 1998-03-17 Lucent Technologies Inc. Process for device fabrication in which a thin layer of cobalt silicide is formed
US6326226B1 (en) * 1997-07-15 2001-12-04 Lg. Philips Lcd Co., Ltd. Method of crystallizing an amorphous film
US7045444B2 (en) 2000-12-19 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device that includes selectively adding a noble gas element
US6858480B2 (en) 2001-01-18 2005-02-22 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
TWI221645B (en) 2001-01-19 2004-10-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
US7115453B2 (en) 2001-01-29 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
JP2002231627A (ja) 2001-01-30 2002-08-16 Semiconductor Energy Lab Co Ltd 光電変換装置の作製方法
US7141822B2 (en) 2001-02-09 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP4993810B2 (ja) * 2001-02-16 2012-08-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5088993B2 (ja) 2001-02-16 2012-12-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7052943B2 (en) 2001-03-16 2006-05-30 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP4718700B2 (ja) * 2001-03-16 2011-07-06 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6812081B2 (en) 2001-03-26 2004-11-02 Semiconductor Energy Laboratory Co.,.Ltd. Method of manufacturing semiconductor device
US7374976B2 (en) 2002-11-22 2008-05-20 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating thin film transistor
US7936040B2 (en) * 2008-10-26 2011-05-03 Koucheng Wu Schottky barrier quantum well resonant tunneling transistor
RU2543685C2 (ru) * 2013-01-14 2015-03-10 Николай Иннокентьевич Плюснин Композитный наноматериал
RU2548225C2 (ru) * 2013-03-06 2015-04-20 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Владивостокский государственный университет экономики и сервиса" (ВГУЭС) Способ получения дисперсной частицы
RU2530456C1 (ru) * 2013-03-06 2014-10-10 Федеральное государственное бюджетное учреждение наук Институт автоматики и процессов управления Дальневосточного отделения Российской академии наук (ИАПУ ДВО РАН) Способ получения слоистого наноматериала
RU2528581C1 (ru) * 2013-03-06 2014-09-20 Федеральное государственное бюджетное учреждение науки Институт автоматики и процессов управления Дальневосточного отделения Российской академии наук (ИАПУ ДВО РАН) Способ получения слоистого наноматериала
FI128093B (en) 2013-07-02 2019-09-13 Ultratech Inc Formation of heteroepitaxial layers with rapid thermal processing to remove lattice dislocations

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH490515A (de) * 1967-11-22 1970-05-15 Battelle Development Corp Verfahren zur Erzeugung von kristallinen Abscheidungen in Form eines Musters auf einer elektrisch isolierenden amorphen, poly- oder einkristallinen Unterlage
FR1593881A (enExample) * 1967-12-12 1970-06-01
US3585088A (en) * 1968-10-18 1971-06-15 Ibm Methods of producing single crystals on supporting substrates
US3796597A (en) * 1970-11-02 1974-03-12 Texas Instruments Inc Method of producing semiconducting monocrystalline silicon on spinel substrates
DE2212295C3 (de) * 1972-03-14 1975-04-17 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung von Silicium- oder Germanium-Epitaxialschichten
US3928092A (en) * 1974-08-28 1975-12-23 Bell Telephone Labor Inc Simultaneous molecular beam deposition of monocrystalline and polycrystalline III(a)-V(a) compounds to produce semiconductor devices
US4179528A (en) * 1977-05-18 1979-12-18 Eastman Kodak Company Method of making silicon device with uniformly thick polysilicon
GB2066299B (en) * 1979-12-19 1983-02-02 Philips Electronic Associated Growing doped iii-v alloy layers by molecular beam epitaxy

Also Published As

Publication number Publication date
FR2534068A1 (fr) 1984-04-06
JPS5983997A (ja) 1984-05-15
CA1209452A (en) 1986-08-12
GB2129019A (en) 1984-05-10
GB2129019B (en) 1986-04-16
HK80886A (en) 1986-10-31
GB8325880D0 (en) 1983-11-02
NL8303341A (nl) 1984-04-16
FR2534068B1 (enExample) 1985-04-19
US4477308A (en) 1984-10-16

Similar Documents

Publication Publication Date Title
DE3335189A1 (de) Verfahren zum herstellen einer heterostruktur
DE3119886C2 (enExample)
DE69217903T2 (de) Halbleiteranordnung auf Basis von Gallium-Nitrid und Verfahren zur Herstellung
DE69231321T2 (de) Verfahren zur Herstellung eines Substrates von SOI-Type mit einer monokristallinen Schicht aus Silizium auf einer isolierenden Schicht
DE69030822T2 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
EP0475378B1 (de) Verfahren zur Herstellung von Substraten für elektronische, elektrooptische und optische Bauelemente
DE68917021T2 (de) Herstellung eines Halbleiterplättchens, das eine III-V-Gruppen-Halbleiterverbindungsschicht auf einem Siliziumsubstrat aufweist.
DE69422229T2 (de) Verfahren zum Herstellen einer Halbleiterdünnschicht und Verfahren zur Herstellung einer Hall-Effekt-Anordnung
DE3587377T2 (de) Verfahren zur herstellung von halbleiteranordnungen unter verwendung von silizium-auf- isolator techniken.
DE3789361T2 (de) Verfahren zur Herstellung eines Artikels, der eine hetero-epitaxische Struktur besitzt.
DE3422750A1 (de) Verfahren zum herstellen einer schicht aus einem mehrbestandteilmaterial
DE69518418T2 (de) Verfahren zur herstellung einer struktur mit niedrigen konzentrationsdefekten mit einer in einem halbleitersubstrat begrabenen oxydschicht
DE10392313T5 (de) Auf Galliumnitrid basierende Vorrichtungen und Herstellungsverfahren
DE19802977A1 (de) Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
DE69320572T2 (de) Dünnfilm-Halbleiteranordnung und Verfahren zur ihrer Herstellung
EP0681314B1 (de) Komposit-Struktur für elektronische Bauteile und Verfahren zu deren Herstellung
DE19751294A1 (de) Halbleiter-Einrichtung und Verfahren zu ihrer Herstellung
DE4009837A1 (de) Verfahren zur herstellung einer halbleitereinrichtung
DE2005271A1 (de) Verfahren zur Vermeidung von Selbstdiffusionsvorgängen durch Ausdiffusion von Störstellensubstanzen aus dem Substrat bbei der Durchführung von epitaktischen ZUchtungsprozessen
DE4313042C2 (de) Diamantschichten mit hitzebeständigen Ohmschen Elektroden und Herstellungsverfahren dafür
DE102018213437A1 (de) Verfahren zur Herstellung von Galliumnitridsubstrat unter Verwendung von Hydriddampfphasenepitaxie
DE69823450T2 (de) Vorrichtung mit einer Oxidschicht auf GaN und Verfahren zur Herstellung
DE102018213434A1 (de) Verfahren zur Herstellung von Galliumnitridsubstrat unter Verwendung der Multiionimplantation
DE69512850T2 (de) Halbleiter-Diamant-Vorrichtung mit verbessertem Metall-Diamant-Kontakt
DE69428750T2 (de) Ohmische Elektrode, Verfahren zur Herstellung und integrierte Schaltung, die diese Elektrode benützt

Legal Events

Date Code Title Description
8127 New person/name/address of the applicant

Owner name: AT & T TECHNOLOGIES, INC., NEW YORK, N.Y., US

8141 Disposal/no request for examination