DE3279494D1 - Method of making integrated circuit device comprising dielectric isolation regions - Google Patents

Method of making integrated circuit device comprising dielectric isolation regions

Info

Publication number
DE3279494D1
DE3279494D1 DE8282108704T DE3279494T DE3279494D1 DE 3279494 D1 DE3279494 D1 DE 3279494D1 DE 8282108704 T DE8282108704 T DE 8282108704T DE 3279494 T DE3279494 T DE 3279494T DE 3279494 D1 DE3279494 D1 DE 3279494D1
Authority
DE
Germany
Prior art keywords
integrated circuit
circuit device
isolation regions
dielectric isolation
making integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282108704T
Other languages
English (en)
Inventor
Hiroshi Momose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3279494D1 publication Critical patent/DE3279494D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Drying Of Semiconductors (AREA)
DE8282108704T 1981-10-14 1982-09-21 Method of making integrated circuit device comprising dielectric isolation regions Expired DE3279494D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56162813A JPS5864044A (ja) 1981-10-14 1981-10-14 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3279494D1 true DE3279494D1 (en) 1989-04-06

Family

ID=15761706

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282108704T Expired DE3279494D1 (en) 1981-10-14 1982-09-21 Method of making integrated circuit device comprising dielectric isolation regions

Country Status (4)

Country Link
US (1) US4463493A (de)
EP (1) EP0076942B1 (de)
JP (1) JPS5864044A (de)
DE (1) DE3279494D1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58100441A (ja) * 1981-12-10 1983-06-15 Toshiba Corp 半導体装置の製造方法
JPS58222558A (ja) * 1982-06-18 1983-12-24 Hitachi Ltd 半導体装置
JPS5978542A (ja) * 1982-10-27 1984-05-07 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の製造方法
CA1204525A (en) * 1982-11-29 1986-05-13 Tetsu Fukano Method for forming an isolation region for electrically isolating elements
JPS6038861A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd 相補型の半導体集積回路装置の製造方法
KR900001267B1 (ko) * 1983-11-30 1990-03-05 후지쓰 가부시끼가이샤 Soi형 반도체 장치의 제조방법
GB8406432D0 (en) * 1984-03-12 1984-04-18 British Telecomm Semiconductor devices
JPS618945A (ja) * 1984-06-25 1986-01-16 Nec Corp 半導体集積回路装置
US4597164A (en) * 1984-08-31 1986-07-01 Texas Instruments Incorporated Trench isolation process for integrated circuit devices
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
NL8402859A (nl) * 1984-09-18 1986-04-16 Philips Nv Werkwijze voor het vervaardigen van submicrongroeven in bijvoorbeeld halfgeleidermateriaal en met deze werkwijze verkregen inrichtingen.
US4578128A (en) * 1984-12-03 1986-03-25 Ncr Corporation Process for forming retrograde dopant distributions utilizing simultaneous outdiffusion of dopants
JPS61194767A (ja) * 1985-02-22 1986-08-29 Nec Corp 相補型ｍｏｓ半導体装置の製造方法
US5450053A (en) * 1985-09-30 1995-09-12 Honeywell Inc. Use of vanadium oxide in microbolometer sensors
US4704849A (en) * 1985-12-17 1987-11-10 Gilbert Zachary R Wheel-mounted weed trimmer
US5300915A (en) * 1986-07-16 1994-04-05 Honeywell Inc. Thermal sensor
IT1213457B (it) * 1986-07-23 1989-12-20 Catania A Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca.
FR2610141B1 (fr) * 1987-01-26 1990-01-19 Commissariat Energie Atomique Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit
JPS63193562A (ja) * 1987-02-06 1988-08-10 Toshiba Corp バイポ−ラトランジスタの製造方法
US4799990A (en) * 1987-04-30 1989-01-24 Ibm Corporation Method of self-aligning a trench isolation structure to an implanted well region
US4791073A (en) * 1987-11-17 1988-12-13 Motorola Inc. Trench isolation method for semiconductor devices
US4876214A (en) * 1988-06-02 1989-10-24 Tektronix, Inc. Method for fabricating an isolation region in a semiconductor substrate
US5286976A (en) * 1988-11-07 1994-02-15 Honeywell Inc. Microstructure design for high IR sensitivity
GB2230134A (en) * 1989-04-05 1990-10-10 Philips Nv A method of manufacturing a semiconductor device
GB2230135A (en) * 1989-04-05 1990-10-10 Koninkl Philips Electronics Nv Dopant diffusion in semiconductor devices
JPH04286361A (ja) * 1991-03-15 1992-10-12 Sony Corp 固体撮像装置
KR0148602B1 (ko) * 1994-11-23 1998-12-01 양승택 반도체 장치의 소자 격리방법
US5696020A (en) * 1994-11-23 1997-12-09 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device isolation region using a trench mask
KR19980034610A (ko) * 1996-11-08 1998-08-05 문정환 반도체장치의 소자격리방법
US5989963A (en) * 1997-07-21 1999-11-23 Advanced Micro Devices, Inc. Method for obtaining a steep retrograde channel profile
US6245649B1 (en) 1999-02-17 2001-06-12 Advanced Micro Devices, Inc. Method for forming a retrograde impurity profile
CN117174583B (zh) * 2023-11-02 2024-01-30 合肥晶合集成电路股份有限公司 半导体结构及其制备方法

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Publication number Priority date Publication date Assignee Title
CH439499A (fr) * 1965-04-07 1967-07-15 Centre Electron Horloger Résistance semiconductrice et procédé pour sa fabrication
US3492174A (en) * 1966-03-19 1970-01-27 Sony Corp Method of making a semiconductor device
CA962372A (en) * 1973-03-27 1975-02-04 Northern Electric Company Isolation of semiconductor devices
US4053349A (en) * 1976-02-02 1977-10-11 Intel Corporation Method for forming a narrow gap
US4061530A (en) * 1976-07-19 1977-12-06 Fairchild Camera And Instrument Corporation Process for producing successive stages of a charge coupled device
JPS5335374A (en) * 1976-09-13 1978-04-01 Nec Corp Production of semiconductor device
DE2705611A1 (de) * 1977-02-10 1978-08-17 Siemens Ag Verfahren zum bedecken einer auf einem substrat befindlichen ersten schicht oder schichtenfolge mit einer weiteren zweiten schicht durch aufsputtern
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
US4362597A (en) * 1981-01-19 1982-12-07 Bell Telephone Laboratories, Incorporated Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices
US4333794A (en) * 1981-04-07 1982-06-08 International Business Machines Corporation Omission of thick Si3 N4 layers in ISA schemes
US4390393A (en) * 1981-11-12 1983-06-28 General Electric Company Method of forming an isolation trench in a semiconductor substrate
JPS58100441A (ja) * 1981-12-10 1983-06-15 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
US4463493A (en) 1984-08-07
JPS5864044A (ja) 1983-04-16
JPS6219061B2 (de) 1987-04-25
EP0076942A2 (de) 1983-04-20
EP0076942B1 (de) 1989-03-01
EP0076942A3 (en) 1986-04-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee