DE3149185A1 - Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen - Google Patents

Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen

Info

Publication number
DE3149185A1
DE3149185A1 DE19813149185 DE3149185A DE3149185A1 DE 3149185 A1 DE3149185 A1 DE 3149185A1 DE 19813149185 DE19813149185 DE 19813149185 DE 3149185 A DE3149185 A DE 3149185A DE 3149185 A1 DE3149185 A1 DE 3149185A1
Authority
DE
Germany
Prior art keywords
silicon nitride
production
layer
channel transistors
implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19813149185
Other languages
German (de)
English (en)
Inventor
Erwin P. Dipl.-Phys. Dr. 8011 Vaterstetten Jacobs
Ulrich Dr. phil. 8000 München Schwabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to DE19813149185 priority Critical patent/DE3149185A1/de
Priority to US06/438,903 priority patent/US4434543A/en
Priority to EP82111357A priority patent/EP0081804B1/de
Priority to DE8282111357T priority patent/DE3273862D1/de
Priority to JP57216789A priority patent/JPS58107663A/ja
Publication of DE3149185A1 publication Critical patent/DE3149185A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H10P30/212—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
DE19813149185 1981-12-11 1981-12-11 Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen Ceased DE3149185A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE19813149185 DE3149185A1 (de) 1981-12-11 1981-12-11 Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US06/438,903 US4434543A (en) 1981-12-11 1982-11-02 Process for producing adjacent tubs implanted with dopant ions in the manufacture of LSI complementary MOS field effect transistors
EP82111357A EP0081804B1 (de) 1981-12-11 1982-12-08 Verfahren zur Herstellung benachbarter mit Dotierstoffionen implantierter Wannen bei der Herstellung von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen
DE8282111357T DE3273862D1 (en) 1981-12-11 1982-12-08 Process for making adjacent ion impurity implanted wells for manufacturing highly integrated complementary mos field effect transistor circuits
JP57216789A JPS58107663A (ja) 1981-12-11 1982-12-09 近接して設けられるド−パントイオン注入盆状区域の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19813149185 DE3149185A1 (de) 1981-12-11 1981-12-11 Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen

Publications (1)

Publication Number Publication Date
DE3149185A1 true DE3149185A1 (de) 1983-06-23

Family

ID=6148526

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19813149185 Ceased DE3149185A1 (de) 1981-12-11 1981-12-11 Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
DE8282111357T Expired DE3273862D1 (en) 1981-12-11 1982-12-08 Process for making adjacent ion impurity implanted wells for manufacturing highly integrated complementary mos field effect transistor circuits

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE8282111357T Expired DE3273862D1 (en) 1981-12-11 1982-12-08 Process for making adjacent ion impurity implanted wells for manufacturing highly integrated complementary mos field effect transistor circuits

Country Status (4)

Country Link
US (1) US4434543A (enExample)
EP (1) EP0081804B1 (enExample)
JP (1) JPS58107663A (enExample)
DE (2) DE3149185A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3334153A1 (de) * 1982-09-24 1984-03-29 Hitachi, Ltd., Tokyo Verfahren zur herstellung einer halbleitereinrichtung
EP0135163B1 (de) * 1983-08-26 1988-05-04 Siemens Aktiengesellschaft Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4574465A (en) * 1982-04-13 1986-03-11 Texas Instruments Incorporated Differing field oxide thicknesses in dynamic memory device
US4507847A (en) * 1982-06-22 1985-04-02 Ncr Corporation Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
DE3304588A1 (de) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von mos-transistoren mit flachen source/drain-gebieten, kurzen kanallaengen und einer selbstjustierten, aus einem metallsilizid bestehenden kontaktierungsebene
DE3314450A1 (de) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4509991A (en) * 1983-10-06 1985-04-09 International Business Machines Corporation Single mask process for fabricating CMOS structure
DE3340560A1 (de) * 1983-11-09 1985-05-15 Siemens AG, 1000 Berlin und 8000 München Verfahren zum gleichzeitigen herstellen von schnellen kurzkanal- und spannungsfesten mos-transistoren in vlsi-schaltungen
US4596068A (en) * 1983-12-28 1986-06-24 Harris Corporation Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4621412A (en) * 1984-09-17 1986-11-11 Sony Corporation Manufacturing a complementary MOSFET
US4677739A (en) * 1984-11-29 1987-07-07 Texas Instruments Incorporated High density CMOS integrated circuit manufacturing process
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
US4929565A (en) * 1986-03-04 1990-05-29 Motorola, Inc. High/low doping profile for twin well process
US4760033A (en) * 1986-04-08 1988-07-26 Siemens Aktiengesellschaft Method for the manufacture of complementary MOS field effect transistors in VLSI technology
JPS62286268A (ja) * 1986-06-04 1987-12-12 Sharp Corp 半導体集積回路装置
EP0250722A3 (de) * 1986-07-04 1988-08-03 Siemens Aktiengesellschaft Verfahren zur Herstellung benachbarter, mit Dotierstoffionen unterschiedlichen Leitungstyps implantierter Wannen für hochintegrierte CMOS-Bauelemente
JPS6410644A (en) * 1987-07-02 1989-01-13 Mitsubishi Electric Corp Manufacture of semiconductor device
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
JPH0727974B2 (ja) * 1988-04-26 1995-03-29 三菱電機株式会社 半導体記憶装置の製造方法
SE461428B (sv) * 1988-06-16 1990-02-12 Ericsson Telefon Ab L M Foerfarande foer att paa ett underlag av halvledarmaterial framstaella en bipolaer transistor eller en bipolaer transistor och en faelteffekttransistor eller en bipolaer transistor och en faelteffekttransistor med en komplementaer faelteffekttransistor och anordningar framstaellda enligt foerfarandena
JPH081930B2 (ja) * 1989-09-11 1996-01-10 株式会社東芝 半導体装置の製造方法
EP0452720A3 (en) * 1990-04-02 1994-10-26 Nat Semiconductor Corp A semiconductor structure and method of its manufacture
US5132241A (en) * 1991-04-15 1992-07-21 Industrial Technology Research Institute Method of manufacturing minimum counterdoping in twin well process
JP3000739B2 (ja) * 1991-08-22 2000-01-17 日本電気株式会社 縦型ｍｏｓ電界効果トランジスタおよびその製造方法
KR950005464B1 (ko) * 1992-02-25 1995-05-24 삼성전자주식회사 반도체장치의 제조방법
US5292681A (en) * 1993-09-16 1994-03-08 Micron Semiconductor, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
KR0146080B1 (ko) * 1995-07-26 1998-08-01 문정환 반도체 소자의 트윈 웰 형성방법
TW336349B (en) * 1997-11-14 1998-07-11 United Microelectronics Corp Process for producing IC well construction
US6391700B1 (en) * 2000-10-17 2002-05-21 United Microelectronics Corp. Method for forming twin-well regions of semiconductor devices
US6348371B1 (en) 2001-03-19 2002-02-19 Taiwan Semiconductor Manufacturing Company Method of forming self-aligned twin wells
DE102005004355B4 (de) * 2005-01-31 2008-12-18 Infineon Technologies Ag Halbleitereinrichtung und Verfahren zu deren Herstellung

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4934086A (enExample) * 1972-07-30 1974-03-29
US3821781A (en) * 1972-11-01 1974-06-28 Ibm Complementary field effect transistors having p doped silicon gates
JPS5125230A (enExample) * 1974-08-26 1976-03-01 Nissan Motor
US4013484A (en) 1976-02-25 1977-03-22 Intel Corporation High density CMOS process
JPS539488A (en) * 1976-07-15 1978-01-27 Hitachi Ltd Production of semiconductor device
JPS5413779A (en) * 1977-07-04 1979-02-01 Toshiba Corp Semiconductor integrated circuit device
JPS5529116A (en) 1978-08-23 1980-03-01 Hitachi Ltd Manufacture of complementary misic
US4244752A (en) 1979-03-06 1981-01-13 Burroughs Corporation Single mask method of fabricating complementary integrated circuits
JPS5643756A (en) * 1979-09-18 1981-04-22 Seiko Epson Corp Manufacture of semiconductor device
US4282648A (en) 1980-03-24 1981-08-11 Intel Corporation CMOS process
US4315781A (en) 1980-04-23 1982-02-16 Hughes Aircraft Company Method of controlling MOSFET threshold voltage with self-aligned channel stop
NL186662C (nl) * 1980-04-29 1992-03-16 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
US4391650A (en) 1980-12-22 1983-07-05 Ncr Corporation Method for fabricating improved complementary metal oxide semiconductor devices
US4684971A (en) * 1981-03-13 1987-08-04 American Telephone And Telegraph Company, At&T Bell Laboratories Ion implanted CMOS devices
US4382827A (en) 1981-04-27 1983-05-10 Ncr Corporation Silicon nitride S/D ion implant mask in CMOS device fabrication
US4385947A (en) 1981-07-29 1983-05-31 Harris Corporation Method for fabricating CMOS in P substrate with single guard ring using local oxidation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3334153A1 (de) * 1982-09-24 1984-03-29 Hitachi, Ltd., Tokyo Verfahren zur herstellung einer halbleitereinrichtung
EP0135163B1 (de) * 1983-08-26 1988-05-04 Siemens Aktiengesellschaft Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen

Also Published As

Publication number Publication date
EP0081804B1 (de) 1986-10-15
JPH0576190B2 (enExample) 1993-10-22
US4434543A (en) 1984-03-06
DE3273862D1 (en) 1986-11-20
EP0081804A3 (en) 1984-07-25
EP0081804A2 (de) 1983-06-22
JPS58107663A (ja) 1983-06-27

Similar Documents

Publication Publication Date Title
DE3149185A1 (de) Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
EP0248988B1 (de) Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen
DE3105118C2 (de) Verfahren zur Herstellung einer integrierten Schaltung mit komplementären bipolaren Transistoren und komplementären Isolierschicht-Gate-Feldeffekttransistoren auf einem gemeinsamen Substrat
EP0073942B1 (de) Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen
EP0123182B1 (de) Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen
DE69615458T2 (de) Dünnfilmtransistor über einem isolierten Halbleitersubstrat und Verfahren zur Herstellung
EP0148342B1 (de) Verfahren zum gleichzeitigen Herstellen von schnellen Kurzkanal- und spannungsfesten MOS-Transistoren in VLSI-Schaltungen
DE3002051C2 (enExample)
EP0247386B1 (de) Lateraltransistor
DE3205022A1 (de) Verfahren zum herstellen einer integrierten halbleiterschaltung
EP0135163B1 (de) Verfahren zum Herstellen von hochintegrierten komplementären MOS-Feldeffekttransistorschaltungen
EP0256315A1 (de) Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
DE3545040C2 (de) Verfahren zur Herstellung einer vergrabenen Schicht und einer Kollektorzone in einer monolithischen Halbleitervorrichtung
EP0204979A1 (de) Verfahren zum gleichzeitigen Herstellen von bipolaren und komplementären MOS-Transistoren auf einem gemeinsamen Siliziumsubstrat
DE4139490A1 (de) Bicmos-vorrichtung und verfahren zur herstellung derselben
EP0006510B1 (de) Verfahren zum Erzeugen aneinander grenzender, unterschiedlich dotierter Siliciumbereiche
DE2542153A1 (de) Halbleiterbaustein und verfahren zur herstellung desselben
EP0157926B1 (de) Verfahren zum Herstellen einer hochintegrierten MOS-Feld-effekttransistorschaltung
DE3788438T2 (de) Methode zur Herstellung von integrierten elektronischen Vorrichtungen, insbesondere Hochspannungs-P-Kanal-MOS-Transistoren.
DE69618077T2 (de) Isolierter vertikaler PNP-Transistor und Verfahren zu seiner Herstellung
DE69735323T2 (de) Halbleiteranordnung und deren Herstellungsverfahren
EP0304541A1 (de) Verfahren zum Herstellen implantierter Wannen und Inseln von integrierten CMOS-Schaltungen
EP0250722A2 (de) Verfahren zur Herstellung benachbarter, mit Dotierstoffionen unterschiedlichen Leitungstyps implantierter Wannen für hochintegrierte CMOS-Bauelemente
WO2003015163A2 (de) Verfahren zum parallelen herstellen eines mos-transistors und eines bipolartransistors
DE2529951A1 (de) Lateraler, bipolarer transistor

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
OR8 Request for search as to paragraph 43 lit. 1 sentence 1 patent law
8131 Rejection