DE3142618C2 - Halbleiteranordnung mit Transistor und Widerstandszone - Google Patents

Halbleiteranordnung mit Transistor und Widerstandszone

Info

Publication number
DE3142618C2
DE3142618C2 DE3142618A DE3142618A DE3142618C2 DE 3142618 C2 DE3142618 C2 DE 3142618C2 DE 3142618 A DE3142618 A DE 3142618A DE 3142618 A DE3142618 A DE 3142618A DE 3142618 C2 DE3142618 C2 DE 3142618C2
Authority
DE
Germany
Prior art keywords
zone
emitter
transistor
region
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3142618A
Other languages
German (de)
English (en)
Other versions
DE3142618A1 (de
Inventor
Didier Jean Raymond Caen Grenier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE3142618A1 publication Critical patent/DE3142618A1/de
Application granted granted Critical
Publication of DE3142618C2 publication Critical patent/DE3142618C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4116—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/10—SRAM devices comprising bipolar components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177—Base regions of bipolar transistors, e.g. BJTs or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • H10D84/615—Combinations of vertical BJTs and one or more of resistors or capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE3142618A 1980-11-07 1981-10-28 Halbleiteranordnung mit Transistor und Widerstandszone Expired DE3142618C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8023825A FR2494041B1 (fr) 1980-11-07 1980-11-07 Element de circuit integre pour memoire bipolaire, son procede de realisation et cellule memoire realisee a l'aide dudit element

Publications (2)

Publication Number Publication Date
DE3142618A1 DE3142618A1 (de) 1982-07-01
DE3142618C2 true DE3142618C2 (de) 1986-01-16

Family

ID=9247788

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3142618A Expired DE3142618C2 (de) 1980-11-07 1981-10-28 Halbleiteranordnung mit Transistor und Widerstandszone

Country Status (9)

Country Link
US (1) US4463370A (https=)
JP (2) JPS57109369A (https=)
CA (1) CA1171552A (https=)
DE (1) DE3142618C2 (https=)
FR (1) FR2494041B1 (https=)
GB (1) GB2087149B (https=)
IE (1) IE52757B1 (https=)
IT (1) IT1140049B (https=)
NL (1) NL186415C (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097659A (ja) * 1983-11-01 1985-05-31 Matsushita Electronics Corp 半導体集積回路
KR100331296B1 (ko) * 1995-12-20 2002-06-20 클라크 3세 존 엠. 에피택셜 핀치 저항기 및 그 형성 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005453A (en) * 1971-04-14 1977-01-25 U.S. Philips Corporation Semiconductor device with isolated circuit elements and method of making
DE2137976C3 (de) * 1971-07-29 1978-08-31 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithischer Speicher und Verfahren zur Herstellung
US4032902A (en) * 1975-10-30 1977-06-28 Fairchild Camera And Instrument Corporation An improved semiconductor memory cell circuit and structure
JPS5379331A (en) * 1976-12-24 1978-07-13 Hitachi Ltd Semiconductor memory cell
JPS5397343A (en) * 1977-02-07 1978-08-25 Hitachi Ltd Semiconductor memory cell
FR2413782A1 (fr) * 1977-12-30 1979-07-27 Radiotechnique Compelec Element de circuit integre destine aux memoires bipolaires a isolement lateral par oxyde
FR2417854A1 (fr) * 1978-02-21 1979-09-14 Radiotechnique Compelec Transistor comportant une zone resistive integree dans sa region d'emetteur
US4246593A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell with polysilicon resistors
US4246592A (en) * 1979-01-02 1981-01-20 Texas Instruments Incorporated High density static memory cell
US4292730A (en) * 1980-03-12 1981-10-06 Harris Corporation Method of fabricating mesa bipolar memory cell utilizing epitaxial deposition, substrate removal and special metallization

Also Published As

Publication number Publication date
IE52757B1 (en) 1988-02-17
JPS6117755U (ja) 1986-02-01
NL186415C (nl) 1990-11-16
JPH0310681Y2 (https=) 1991-03-15
IE812582L (en) 1982-05-07
JPS57109369A (en) 1982-07-07
DE3142618A1 (de) 1982-07-01
IT8124861A0 (it) 1981-11-04
NL186415B (nl) 1990-06-18
GB2087149A (en) 1982-05-19
CA1171552A (en) 1984-07-24
US4463370A (en) 1984-07-31
GB2087149B (en) 1984-07-18
FR2494041A1 (fr) 1982-05-14
IT1140049B (it) 1986-09-24
NL8104961A (nl) 1982-06-01
FR2494041B1 (fr) 1987-01-23

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee