DE2738049A1 - Integrierte halbleiterschaltungsanordnung - Google Patents

Integrierte halbleiterschaltungsanordnung

Info

Publication number
DE2738049A1
DE2738049A1 DE19772738049 DE2738049A DE2738049A1 DE 2738049 A1 DE2738049 A1 DE 2738049A1 DE 19772738049 DE19772738049 DE 19772738049 DE 2738049 A DE2738049 A DE 2738049A DE 2738049 A1 DE2738049 A1 DE 2738049A1
Authority
DE
Germany
Prior art keywords
semiconductor circuit
circuit arrangement
arrangement according
epitaxial layer
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19772738049
Other languages
German (de)
English (en)
Inventor
Martin J Alter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of DE2738049A1 publication Critical patent/DE2738049A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE19772738049 1976-09-03 1977-08-24 Integrierte halbleiterschaltungsanordnung Ceased DE2738049A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/720,550 US4149177A (en) 1976-09-03 1976-09-03 Method of fabricating conductive buried regions in integrated circuits and the resulting structures

Publications (1)

Publication Number Publication Date
DE2738049A1 true DE2738049A1 (de) 1978-03-09

Family

ID=24894399

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19772738049 Ceased DE2738049A1 (de) 1976-09-03 1977-08-24 Integrierte halbleiterschaltungsanordnung

Country Status (6)

Country Link
US (1) US4149177A (https=)
JP (1) JPS5331984A (https=)
CA (1) CA1085064A (https=)
DE (1) DE2738049A1 (https=)
FR (1) FR2363889A1 (https=)
GB (1) GB1577420A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2443744A1 (fr) * 1978-12-04 1980-07-04 Fairchild Camera Instr Co Procede de fabrication d'un transistor a effet de champ a porte a barriere de schottky

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2413782A1 (fr) * 1977-12-30 1979-07-27 Radiotechnique Compelec Element de circuit integre destine aux memoires bipolaires a isolement lateral par oxyde
US4231056A (en) * 1978-10-20 1980-10-28 Harris Corporation Moat resistor ram cell
JPS5799771A (en) * 1980-12-12 1982-06-21 Hitachi Ltd Semiconductor device
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
US4961102A (en) * 1982-01-04 1990-10-02 Shideler Jay A Junction programmable vertical transistor with high performance transistor
JPS58199537A (ja) * 1982-05-14 1983-11-19 Matsushita Electric Ind Co Ltd 高抵抗半導体層の製造方法
US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
US5023200A (en) * 1988-11-22 1991-06-11 The United States Of America As Represented By The United States Department Of Energy Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
DE2215351A1 (de) * 1971-04-03 1972-10-12 Philips Nv Halbleiteranordnung und Verfahren zur Herstellung derselben

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
JPS4975280A (https=) * 1972-11-24 1974-07-19
US3975752A (en) * 1973-04-04 1976-08-17 Harris Corporation Junction field effect transistor
US3962717A (en) * 1974-10-29 1976-06-08 Fairchild Camera And Instrument Corporation Oxide isolated integrated injection logic with selective guard ring

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
DE2215351A1 (de) * 1971-04-03 1972-10-12 Philips Nv Halbleiteranordnung und Verfahren zur Herstellung derselben

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Solid-State Circuits, Bd. SC-8, No. 5, 1973, S. 373-380 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2443744A1 (fr) * 1978-12-04 1980-07-04 Fairchild Camera Instr Co Procede de fabrication d'un transistor a effet de champ a porte a barriere de schottky

Also Published As

Publication number Publication date
US4149177A (en) 1979-04-10
CA1085064A (en) 1980-09-02
JPS5331984A (en) 1978-03-25
GB1577420A (en) 1980-10-22
JPS6224944B2 (https=) 1987-05-30
FR2363889B1 (https=) 1983-01-14
FR2363889A1 (fr) 1978-03-31

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Legal Events

Date Code Title Description
OD Request for examination
8131 Rejection