GB1577420A - Semiconductor structures with conductive buried regions - Google Patents

Semiconductor structures with conductive buried regions Download PDF

Info

Publication number
GB1577420A
GB1577420A GB24570/77A GB2457077A GB1577420A GB 1577420 A GB1577420 A GB 1577420A GB 24570/77 A GB24570/77 A GB 24570/77A GB 2457077 A GB2457077 A GB 2457077A GB 1577420 A GB1577420 A GB 1577420A
Authority
GB
United Kingdom
Prior art keywords
semiconductor structure
epitaxial layer
region
conductivity type
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB24570/77A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of GB1577420A publication Critical patent/GB1577420A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
GB24570/77A 1976-09-03 1977-06-13 Semiconductor structures with conductive buried regions Expired GB1577420A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/720,550 US4149177A (en) 1976-09-03 1976-09-03 Method of fabricating conductive buried regions in integrated circuits and the resulting structures

Publications (1)

Publication Number Publication Date
GB1577420A true GB1577420A (en) 1980-10-22

Family

ID=24894399

Family Applications (1)

Application Number Title Priority Date Filing Date
GB24570/77A Expired GB1577420A (en) 1976-09-03 1977-06-13 Semiconductor structures with conductive buried regions

Country Status (6)

Country Link
US (1) US4149177A (https=)
JP (1) JPS5331984A (https=)
CA (1) CA1085064A (https=)
DE (1) DE2738049A1 (https=)
FR (1) FR2363889A1 (https=)
GB (1) GB1577420A (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2413782A1 (fr) * 1977-12-30 1979-07-27 Radiotechnique Compelec Element de circuit integre destine aux memoires bipolaires a isolement lateral par oxyde
US4231056A (en) * 1978-10-20 1980-10-28 Harris Corporation Moat resistor ram cell
US4277882A (en) * 1978-12-04 1981-07-14 Fairchild Camera And Instrument Corporation Method of producing a metal-semiconductor field-effect transistor
JPS5799771A (en) * 1980-12-12 1982-06-21 Hitachi Ltd Semiconductor device
US4624046A (en) * 1982-01-04 1986-11-25 Fairchild Camera & Instrument Corp. Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM
US4961102A (en) * 1982-01-04 1990-10-02 Shideler Jay A Junction programmable vertical transistor with high performance transistor
JPS58199537A (ja) * 1982-05-14 1983-11-19 Matsushita Electric Ind Co Ltd 高抵抗半導体層の製造方法
US4549927A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
US5023200A (en) * 1988-11-22 1991-06-11 The United States Of America As Represented By The United States Department Of Energy Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
NL170901C (nl) * 1971-04-03 1983-01-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
JPS4975280A (https=) * 1972-11-24 1974-07-19
US3975752A (en) * 1973-04-04 1976-08-17 Harris Corporation Junction field effect transistor
US3962717A (en) * 1974-10-29 1976-06-08 Fairchild Camera And Instrument Corporation Oxide isolated integrated injection logic with selective guard ring

Also Published As

Publication number Publication date
US4149177A (en) 1979-04-10
CA1085064A (en) 1980-09-02
JPS5331984A (en) 1978-03-25
JPS6224944B2 (https=) 1987-05-30
FR2363889B1 (https=) 1983-01-14
DE2738049A1 (de) 1978-03-09
FR2363889A1 (fr) 1978-03-31

Similar Documents

Publication Publication Date Title
US5140388A (en) Vertical metal-oxide semiconductor devices
US4033797A (en) Method of manufacturing a complementary metal-insulation-semiconductor circuit
US6798037B2 (en) Isolation trench structure for integrated devices
US4375645A (en) Semiconductor device and a method of producing the same
US4228450A (en) Buried high sheet resistance structure for high density integrated circuits with reach through contacts
US3509433A (en) Contacts for buried layer in a dielectrically isolated semiconductor pocket
JPH0719838B2 (ja) 半導体装置およびその製造方法
US4567641A (en) Method of fabricating semiconductor devices having a diffused region of reduced length
US4051506A (en) Complementary semiconductor device
US4425379A (en) Polycrystalline silicon Schottky diode array
US4433471A (en) Method for the formation of high density memory cells using ion implantation techniques
US4198649A (en) Memory cell structure utilizing conductive buried regions
US4149177A (en) Method of fabricating conductive buried regions in integrated circuits and the resulting structures
EP0078220B1 (en) Polycrystalline silicon interconnections for bipolar transistor flip-flop
CA1126875A (en) Dielectrically-isolated integrated circuit complementary transistors for high voltage use
US4118728A (en) Integrated circuit structures utilizing conductive buried regions
JP3074708B2 (ja) 高出力用集積回路のための半導体構造
EP0078571A1 (en) Semiconductor device and method of manufacturing the same
KR910006699B1 (ko) 반도체 장치
US4720739A (en) Dense, reduced leakage CMOS structure
SU773793A1 (ru) Способ изготовлени полупроводниковых интегральных бипол рных схем
JPH02246264A (ja) 半導体装置およびその製造方法
US4197143A (en) Method of making a junction field-effect transistor utilizing a conductive buried region
US4692784A (en) Dielectric insulation type semiconductor integrated circuit having low withstand voltage devices and high withstand voltage devices
US6083800A (en) Method for fabricating high voltage semiconductor device

Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19950613