DE2729171C2 - Verfahren zur Herstellung einer integrierten Schaltung - Google Patents
Verfahren zur Herstellung einer integrierten SchaltungInfo
- Publication number
- DE2729171C2 DE2729171C2 DE2729171A DE2729171A DE2729171C2 DE 2729171 C2 DE2729171 C2 DE 2729171C2 DE 2729171 A DE2729171 A DE 2729171A DE 2729171 A DE2729171 A DE 2729171A DE 2729171 C2 DE2729171 C2 DE 2729171C2
- Authority
- DE
- Germany
- Prior art keywords
- openings
- masking layer
- layer
- etched
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000000873 masking effect Effects 0.000 claims description 40
- 239000002019 doping agent Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 36
- 235000012239 silicon dioxide Nutrition 0.000 description 18
- 239000000377 silicon dioxide Substances 0.000 description 18
- 238000009792 diffusion process Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000010405 reoxidation reaction Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/047—Emitter dip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Respiratory Apparatuses And Protective Means (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/700,432 US4021270A (en) | 1976-06-28 | 1976-06-28 | Double master mask process for integrated circuit manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE2729171A1 DE2729171A1 (de) | 1977-12-29 |
| DE2729171C2 true DE2729171C2 (de) | 1983-03-03 |
Family
ID=24813479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE2729171A Expired DE2729171C2 (de) | 1976-06-28 | 1977-06-28 | Verfahren zur Herstellung einer integrierten Schaltung |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4021270A (enExample) |
| JP (1) | JPS532091A (enExample) |
| DE (1) | DE2729171C2 (enExample) |
| FR (1) | FR2357063A1 (enExample) |
| GB (1) | GB1535493A (enExample) |
| HK (1) | HK981A (enExample) |
Families Citing this family (29)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4153487A (en) * | 1974-12-27 | 1979-05-08 | Tokyo Shibaura Electric Co., Ltd. | Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques |
| US4151019A (en) * | 1974-12-27 | 1979-04-24 | Tokyo Shibaura Electric Co., Ltd. | Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques |
| US4178190A (en) * | 1975-06-30 | 1979-12-11 | Rca Corporation | Method of making a bipolar transistor with high-low emitter impurity concentration |
| US4113512A (en) * | 1976-10-28 | 1978-09-12 | International Business Machines Corporation | Technique for preventing forward biased epi-isolation degradation |
| US4135954A (en) * | 1977-07-12 | 1979-01-23 | International Business Machines Corporation | Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers |
| US4110126A (en) * | 1977-08-31 | 1978-08-29 | International Business Machines Corporation | NPN/PNP Fabrication process with improved alignment |
| US4159915A (en) * | 1977-10-25 | 1979-07-03 | International Business Machines Corporation | Method for fabrication vertical NPN and PNP structures utilizing ion-implantation |
| US4155778A (en) * | 1977-12-30 | 1979-05-22 | International Business Machines Corporation | Forming semiconductor devices having ion implanted and diffused regions |
| US4118250A (en) * | 1977-12-30 | 1978-10-03 | International Business Machines Corporation | Process for producing integrated circuit devices by ion implantation |
| US4228451A (en) * | 1978-07-21 | 1980-10-14 | Monolithic Memories, Inc. | High resistivity semiconductor resistor device |
| JPS55138267A (en) * | 1979-04-12 | 1980-10-28 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit containing resistance element |
| US4267012A (en) * | 1979-04-30 | 1981-05-12 | Fairchild Camera & Instrument Corp. | Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer |
| US4257826A (en) * | 1979-10-11 | 1981-03-24 | Texas Instruments Incorporated | Photoresist masking in manufacture of semiconductor device |
| JPS5685848A (en) * | 1979-12-15 | 1981-07-13 | Toshiba Corp | Manufacture of bipolar integrated circuit |
| US4429321A (en) * | 1980-10-23 | 1984-01-31 | Canon Kabushiki Kaisha | Liquid jet recording device |
| US4416055A (en) * | 1981-12-04 | 1983-11-22 | Gte Laboratories Incorporated | Method of fabricating a monolithic integrated circuit structure |
| US4648909A (en) * | 1984-11-28 | 1987-03-10 | Fairchild Semiconductor Corporation | Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits |
| IT1188465B (it) * | 1986-03-27 | 1988-01-14 | Sgs Microelettronica Spa | Rpocedimento per la fabbricazione di circuiti integrati a semiconduttore includenti dispositiv cmos e dispositivi elettronici ad alta tensione |
| EP0255970B1 (en) * | 1986-08-08 | 1993-12-15 | Philips Electronics Uk Limited | A method of manufacturing an insulated gate field effect transistor |
| US4898837A (en) * | 1987-11-19 | 1990-02-06 | Sanyo Electric Co., Ltd. | Method of fabricating a semiconductor integrated circuit |
| US5141881A (en) * | 1989-04-20 | 1992-08-25 | Sanyo Electric Co., Ltd. | Method for manufacturing a semiconductor integrated circuit |
| JPH06101540B2 (ja) * | 1989-05-19 | 1994-12-12 | 三洋電機株式会社 | 半導体集積回路の製造方法 |
| GB2237445B (en) * | 1989-10-04 | 1994-01-12 | Seagate Microelectron Ltd | A semiconductor device fabrication process |
| US5179030A (en) * | 1991-04-26 | 1993-01-12 | Unitrode Corporation | Method of fabricating a buried zener diode simultaneously with other semiconductor devices |
| FR2687843A1 (fr) * | 1992-02-24 | 1993-08-27 | Motorola Semiconducteurs | Transistor bipolaire lateral pnp et procede de fabrication. |
| WO1996030936A1 (en) * | 1995-03-27 | 1996-10-03 | Micrel, Incorporated | Self-alignment technique for semiconductor devices |
| US5702959A (en) * | 1995-05-31 | 1997-12-30 | Texas Instruments Incorporated | Method for making an isolated vertical transistor |
| FR2785089B1 (fr) * | 1998-10-23 | 2002-03-01 | St Microelectronics Sa | Realisation de mur d'isolement |
| EP1296374B1 (en) * | 2001-09-14 | 2012-09-05 | STMicroelectronics Srl | Process for bonding and electrically connecting microsystems integrated in several distinct substrates |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3479237A (en) * | 1966-04-08 | 1969-11-18 | Bell Telephone Labor Inc | Etch masks on semiconductor surfaces |
| DE1764358B1 (de) * | 1967-05-26 | 1971-09-30 | Tokyo Shibaura Electric Co | Verfahren zum herstellen eines halbleiterbauelementes |
| NL7004130A (enExample) * | 1969-04-03 | 1970-10-06 | ||
| US3673679A (en) * | 1970-12-01 | 1972-07-04 | Texas Instruments Inc | Complementary insulated gate field effect devices |
| JPS4873085A (enExample) * | 1971-12-29 | 1973-10-02 | ||
| DE2314260A1 (de) * | 1972-05-30 | 1973-12-13 | Ibm | Ladungsgekoppelte halbleiteranordnung und verfahren zu ihrer herstellung |
| US3771218A (en) * | 1972-07-13 | 1973-11-13 | Ibm | Process for fabricating passivated transistors |
| US3793088A (en) * | 1972-11-15 | 1974-02-19 | Bell Telephone Labor Inc | Compatible pnp and npn devices in an integrated circuit |
| US3868274A (en) * | 1974-01-02 | 1975-02-25 | Gen Instrument Corp | Method for fabricating MOS devices with a multiplicity of thresholds on a semiconductor substrate |
-
1976
- 1976-06-28 US US05/700,432 patent/US4021270A/en not_active Expired - Lifetime
-
1977
- 1977-05-30 GB GB22832/77A patent/GB1535493A/en not_active Expired
- 1977-06-14 JP JP6950977A patent/JPS532091A/ja active Pending
- 1977-06-28 DE DE2729171A patent/DE2729171C2/de not_active Expired
- 1977-06-28 FR FR7719862A patent/FR2357063A1/fr active Granted
-
1981
- 1981-01-15 HK HK9/81A patent/HK981A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| FR2357063B1 (enExample) | 1982-02-19 |
| JPS532091A (en) | 1978-01-10 |
| FR2357063A1 (fr) | 1978-01-27 |
| GB1535493A (en) | 1978-12-13 |
| US4021270A (en) | 1977-05-03 |
| HK981A (en) | 1981-01-23 |
| DE2729171A1 (de) | 1977-12-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OD | Request for examination | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition |