DE2640465A1 - Verfahren zur herstellung dotierter zonen in einem halbleitersubstrat - Google Patents

Verfahren zur herstellung dotierter zonen in einem halbleitersubstrat

Info

Publication number
DE2640465A1
DE2640465A1 DE19762640465 DE2640465A DE2640465A1 DE 2640465 A1 DE2640465 A1 DE 2640465A1 DE 19762640465 DE19762640465 DE 19762640465 DE 2640465 A DE2640465 A DE 2640465A DE 2640465 A1 DE2640465 A1 DE 2640465A1
Authority
DE
Germany
Prior art keywords
semiconductor substrate
layer
insulating layer
polycrystalline silicon
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19762640465
Other languages
German (de)
English (en)
Other versions
DE2640465C2 (enExample
Inventor
Helmuth Dipl Phys Dr Murrmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE19762640465 priority Critical patent/DE2640465A1/de
Publication of DE2640465A1 publication Critical patent/DE2640465A1/de
Application granted granted Critical
Publication of DE2640465C2 publication Critical patent/DE2640465C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Bipolar Transistors (AREA)
DE19762640465 1976-09-08 1976-09-08 Verfahren zur herstellung dotierter zonen in einem halbleitersubstrat Granted DE2640465A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19762640465 DE2640465A1 (de) 1976-09-08 1976-09-08 Verfahren zur herstellung dotierter zonen in einem halbleitersubstrat

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19762640465 DE2640465A1 (de) 1976-09-08 1976-09-08 Verfahren zur herstellung dotierter zonen in einem halbleitersubstrat

Publications (2)

Publication Number Publication Date
DE2640465A1 true DE2640465A1 (de) 1978-03-09
DE2640465C2 DE2640465C2 (enExample) 1989-06-15

Family

ID=5987461

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762640465 Granted DE2640465A1 (de) 1976-09-08 1976-09-08 Verfahren zur herstellung dotierter zonen in einem halbleitersubstrat

Country Status (1)

Country Link
DE (1) DE2640465A1 (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2445023A1 (fr) * 1978-12-23 1980-07-18 Vlsi Technology Res Ass Procede de fabrication d'un circuit integre contenant du silicium polycristallin
EP0029548A1 (de) * 1979-11-21 1981-06-03 Siemens Aktiengesellschaft Verfahren zum Herstellen eines Bipolartransistors
EP0029887A1 (de) * 1979-12-03 1981-06-10 International Business Machines Corporation Verfahren zum Herstellen eines vertikalen PNP-Transistors und so hergestellter Transistor
EP0034910B1 (en) * 1980-02-18 1985-01-09 VLSI Technology Research Association A method of manufacturing a semiconductor device, and a device so manufactured
EP0477995A1 (en) * 1985-04-01 1992-04-01 Fairchild Semiconductor Corporation Process for forming CMOS and bipolar devices on the same substrate
US5340762A (en) * 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2225374A1 (de) * 1971-05-28 1973-06-20 Fujitsu Ltd Halbleitervorrichtung und verfahren zu ihrer herstellung

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2225374A1 (de) * 1971-05-28 1973-06-20 Fujitsu Ltd Halbleitervorrichtung und verfahren zu ihrer herstellung

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2445023A1 (fr) * 1978-12-23 1980-07-18 Vlsi Technology Res Ass Procede de fabrication d'un circuit integre contenant du silicium polycristallin
EP0029548A1 (de) * 1979-11-21 1981-06-03 Siemens Aktiengesellschaft Verfahren zum Herstellen eines Bipolartransistors
EP0029887A1 (de) * 1979-12-03 1981-06-10 International Business Machines Corporation Verfahren zum Herstellen eines vertikalen PNP-Transistors und so hergestellter Transistor
EP0034910B1 (en) * 1980-02-18 1985-01-09 VLSI Technology Research Association A method of manufacturing a semiconductor device, and a device so manufactured
EP0477995A1 (en) * 1985-04-01 1992-04-01 Fairchild Semiconductor Corporation Process for forming CMOS and bipolar devices on the same substrate
US5340762A (en) * 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell

Also Published As

Publication number Publication date
DE2640465C2 (enExample) 1989-06-15

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8125 Change of the main classification

Ipc: H01L 21/225

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee