DE2640465A1 - Semiconductor substrate doped zone prodn. - applying non-doped silicon layer which is coated with two insulating layers partially removed leaving bare zones for doping - Google Patents
Semiconductor substrate doped zone prodn. - applying non-doped silicon layer which is coated with two insulating layers partially removed leaving bare zones for dopingInfo
- Publication number
- DE2640465A1 DE2640465A1 DE19762640465 DE2640465A DE2640465A1 DE 2640465 A1 DE2640465 A1 DE 2640465A1 DE 19762640465 DE19762640465 DE 19762640465 DE 2640465 A DE2640465 A DE 2640465A DE 2640465 A1 DE2640465 A1 DE 2640465A1
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- Germany
- Prior art keywords
- semiconductor substrate
- layer
- insulating layer
- polycrystalline silicon
- areas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
Abstract
Description
Verfahren zur Herstellung dotierter Zonen in einem Halbleiter-Process for the production of doped zones in a semiconductor
Substrat.Substrate.
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung dotierter Zonen in einem Halbleitersubstrat, bei dem die Dotierung in den gewünschten Zonen durch eine auf dem Halbleitersubstrat befindliche polykristalline Siliciumschicht in das Halbleitersubstrat eingebracht wird (sogenannte Polysiltechnik).The present invention relates to a method for producing doped Zones in a semiconductor substrate in which the doping is in the desired zones by a polycrystalline silicon layer located on the semiconductor substrate is introduced into the semiconductor substrate (so-called polysil technology).
Bei der beispielsweise aus iedm Technical Digest, Internat.For example, from iedm Technical Digest, Internat.
Electron. Devices Meeting (1975), Katalog-Nr. 75 CH 1023-1 E bekanntgewordenen Polysiltechnik wird zur Herstellung des Emitters von Transistoren nach dem Öffnen eines Fensters in einer auf einem Halbleitersubstrat befindlichen Isolierschicht (beispielsweise Siliciumdioxid-Schicht) eine undotierte Schicht aus polykristallinem Silicium über der auf dem Halbleitersubstrat befindlichen Isolierschicht abgeschieden. Der Emitter wird sodann durch diese Schicht aus polykristallinem Silicium in das Halbleitersubstrat eindiffundiert. Danach wird die Schicht aus polykristallinem Silicium mittels fotolithografischer Verfahren in der Weise strukturgeätzt, daß nur ein Deckel der Schicht aus polykristallinem Silicium über dem Emitterfenster in der Isolierschicht verbleibt.Electron. Devices Meeting (1975), Catalog No. 75 CH 1023-1 E became known Polysiltechnik is used to manufacture the emitter of transistors after opening a window in an insulating layer located on a semiconductor substrate (for example silicon dioxide layer) an undoped layer of polycrystalline Silicon deposited over the insulating layer located on the semiconductor substrate. The emitter is then inserted through this layer of polycrystalline silicon into the Semiconductor substrate diffused. After that the layer is made of polycrystalline Silicon is etched structure by means of photolithographic processes in such a way that just a lid of the layer of polycrystalline silicon over the emitter window remains in the insulating layer.
In der in der Planartechnik üblichen Weise wird anschließend das Kontaktfenster für den Anschluß der Basiszone in die das Halbleitersubstrat bedeckende Isolierschicht (beispielsweise Silicium- dioxid-Schicht) eingeätzt. Bei der anschließend aufzubringenden Metallisierung zur Kontaktierung der Transistorzonen liegt eine Topologie der Oberfläche vor, welche Höhenunterschiede von 0,5 - 1,0/um aufweist.The contact window is then made in the manner customary in planar technology for connecting the base zone into the insulating layer covering the semiconductor substrate (e.g. silicon dioxide layer). In the subsequent metallization to be applied for contacting the transistor zones is a Topology of the surface, which has height differences of 0.5 - 1.0 / µm.
Bei dieser Technik ist es noch immer erforderlich, zwei Masken zu verwenden, wobei eine Maske Fenster für die Emitterzone und den Kollektorkontakt und eine zweite Maske mindestens ein Fenster für den Basiskontakt besitzt. Daraus ergibt sich die Notwendigkeit einer genauen Justierung der beiden Masken, was in der Praxis zu Justierungsfehlern führen kann, die im ungünstigsten Fall sogar zu einem Kurzschluß etwa zwischen Emitterzone und Basiskontakt führen können.This technique still requires two masks to be applied Use a mask window for the emitter zone and the collector contact and a second mask has at least one window for the base contact. From it there is a need for a precise adjustment of the two masks, which is shown in in practice can lead to adjustment errors, which in the worst case can even lead to a short circuit between the emitter zone and the base contact.
Weiterhin führt auch die mehrmalige Herstellung von Kontaktfenstern in der das Halbleitersubstrat bedeckenden Isolierschicht (Siliciumdioxid-Schicht) zu topologisch stark strukturierten Oberflächen, was für die Aufbringung der zur Kontaktierung notwendigen Metallisierungen nachteilig ist.Furthermore, the repeated production of contact windows also leads in the insulating layer (silicon dioxide layer) covering the semiconductor substrate too topologically structured surfaces, which is important for the application of the Contacting necessary metallizations is disadvantageous.
Der vorliegenden Erfindung liegt die Aufgabe zugrunde, ein Verfahren zur Herstellung dotierter Zonen in einem Halbleitersubstrat anzugeben, bei dem die vorgenannten Nachteile aufgrund von Fehljustierungen mehrerer Masken und einer topologisch stark strukturierten Oberfläche für die aufzubringenden Metallisierungen vermieden werden.The present invention is based on the object of a method specify for the production of doped zones in a semiconductor substrate, in which the aforementioned disadvantages due to misalignments of several masks and one topological heavily structured surface avoided for the metallizations to be applied will.
Diese Aufgabe wird bei einem Verfahren der eingangs genannten Art erfindungsgemäß dadurch gelöst, daß auf die Oberfläche des Halbleitersubstrats zunächst eine erste Isolierschicht aufgebracht wird, in der entsprechend der Anzahl der herzustellenden dotierten Zonen Fenster hergestellt werden, daß auf die erste Isolierschicht und in die in ihr befindlichen Fenster eine Schicht aus polykristallinem Silicium aufgebracht wird, daß auf die Schicht aus polykristallinem Silicium eine zweite Isolierschicht aufgebracht und teilweise so wieder entfernt wird, daß nur noch über den Bereichen, unter denen die herzustellenden dotierten Zonen entstehen sollen, Teile der zweiten Isolierschicht auf der Schicht aus polykristallinem Silicium verbleiben, daß die nicht von Teilen der zweiten Isolierschicht bedeckten Bereiche der Schicht aus polykristallinem Silicium in Siliciumoxid übergeführt werden, und daß zum Einbringen von Dotierungen in die verbliebenen Bereiche aus polykristallinem Silicium sowie zum weiteren Einbringen der Dotierungen in das Halbleitersubstrat die über diesen Bereichen aus polykristallinem Silicium befindlichen Teile der zweiten Isolierschicht entfernt werden.This task is performed in a method of the type mentioned at the beginning according to the invention achieved in that initially on the surface of the semiconductor substrate a first insulating layer is applied, in which corresponding to the number of to be produced doped zones that are made on the first insulating layer and windows A layer of polycrystalline silicon is applied to the window located in it that on the layer of polycrystalline silicon a second insulating layer is applied and partially removed again so that only over the Areas under which the doped zones to be produced are to arise, parts the second insulating layer remain on the layer of polycrystalline silicon, that the areas of the layer not covered by parts of the second insulating layer from polycrystalline silicon are converted into silicon oxide, and that for introduction of doping in the remaining areas of polycrystalline silicon and for further introduction of the doping into the semiconductor substrate via this Areas of polycrystalline silicon located parts of the second insulating layer removed.
Ausgestaltungen des Erfindungsgedankens sind in Unteransprüchen gekennzeichnet.Refinements of the inventive concept are characterized in the subclaims.
Die Erfindung wird im folgenden anhand der Figuren der Zeichnung am Beispiel der Herstellung eines Transistors näher erläutert.The invention is described below with reference to the figures of the drawing on Example of the manufacture of a transistor explained in more detail.
Die Fig. 1 - 5 zeigen dabei aufeinanderfolgende Herstellungsschritte bis zu einem fertigen Transistor, wobei jeweils gleiche Elemente mit gleichen Bezugszeichen versehen sind.FIGS. 1-5 show successive manufacturing steps up to a finished transistor, the same elements with the same reference numerals are provided.
Gemäß Fig. 1 beginnt das Verfahren zur Herstellung eines Transistors mit einem Halbleitersubstrat 1 eines Leitungstyps (beispielsweise n), in das in der in der Planartechnik üblichen Weise eine Basiszone 2 des anderen Leitungstyps (beispielsweise p) eindiffundiert wird. Auf das Halbleitersubstrat 1 mit der in ihm befindlichen Basiszone 2 wird sodann eine Isolierschicht 3 aufgebracht, welche aus Siliciumdioxid oder Siliciumnitrid bestehen kann. In dieser Isolierschicht 3 werden Fenster 4, 5, 6 hergestellt, durch welche die Dotierungen für den Kollektorkontakt, den Basiskontakt und die Emitterzone in das Halbleitersubstrat 1 eingebracht werden.According to Fig. 1, the method for manufacturing a transistor begins with a semiconductor substrate 1 of a conductivity type (for example n) into which in a base zone 2 of the other conductivity type in the manner customary in planar technology (for example p) is diffused. On the semiconductor substrate 1 with the in an insulating layer 3 is then applied to it located base zone 2, which may consist of silicon dioxide or silicon nitride. In this insulating layer 3 windows 4, 5, 6 are made through which the doping for the collector contact, the base contact and the emitter zone are introduced into the semiconductor substrate 1.
Auf die Isolierschicht 3 mit den in ihr befindlichen Fenstern 4, 5, 6 wird sodann eine Schicht 7 aus polykristallinem, undotiertem Silicium aufgebracht. Auf diese Schicht 7 aus polykristallinem Silicium wird anschließend eine zweite Isolierschicht 8 aufgebracht, welche aus Siliciumnitrid bestehen kann.On the insulating layer 3 with the windows 4, 5, 6 a layer 7 of polycrystalline, undoped silicon is then applied. On this layer 7 of polycrystalline Silicon is subsequently a second insulating layer 8 is applied, which can consist of silicon nitride.
Gemäß Fig. 2 wird nun die Siliciumnitridschicht 8 mit Hilfe einer geeigneten Maske so strukturgeätzt, daß Teile 81, 82, 83 über den Bereichen eines Kollektorkontaktes, eines Basiskontaktes und einer Emitterzone verbleiben. Das gesamte System wird danach einer thermischen oder anodischen Oxydation unterzogen, so daß die freiliegenden Bereiche der Schicht 7 aus polykristallinem Silicium in Bereiche 74, 75, 76, 77 aus Siliciumoxid überführt werden.According to FIG. 2, the silicon nitride layer 8 is now with the aid of a suitable mask structure etched so that parts 81, 82, 83 over the areas of a Collector contact, a base contact and an emitter zone remain. The entire The system is then subjected to thermal or anodic oxidation so that the exposed areas of the layer 7 of polycrystalline silicon in areas 74, 75, 76, 77 are transferred from silicon oxide.
In einem nachfolgenden, aus Fig.3 ersichtlichen Schritt wird sodann der Teil 82 aus Siliciumnitrid über dem Bereich 72 aus polykristallinem Silicium entfernt und durch diesen Bereich 72 aus polykristallinem Silicium ein Dotierungsstoff in das Halbleitersubstrat 1 eingebracht, so daß eine Zone 10 entsteht, welche als Basiskontakt dient. Das Einbringen (Diffundieren oder Implantieren) des Dotierungsstoffes (beispielsweise Bor> ist schematisch durch Pfeile angedeutet, welche mit A bezeichnet sind.In a subsequent step that can be seen from FIG the portion 82 of silicon nitride over the portion 72 of polycrystalline silicon and through this region 72 of polycrystalline silicon a dopant introduced into the semiconductor substrate 1, so that a zone 10 is formed, which as Basic contact serves. The introduction (diffusion or implantation) of the dopant (for example boron> is indicated schematically by arrows denoted by A. are.
In einem folgenden, anhand von Fig. 4 dargestellten Verfahrensschritt werden auch die Teile 81 und 83 über den Bereichen 71 und 73 aus polykristallinem Silicium entfernt. Der über dem Basiskontakt 10 liegende Bereich 72 aus polykristallinem Silicium wird mit einer maskierenden Lackschicht 50 abgedeckt. Sodann werden durch die Bereiche 71 und 73 aus polykristallinem Silicium zur Herstellung einer Kollektorkontaktzone 40 und einer Emitterzone 41 weitere Dotierungen eingebracht (implantiert). Dieser Dotierungsschritt ist in Fig. 4 schematisch durch Pfeile angedeutet, welche mit B bezeichnet sind.In a subsequent method step illustrated with reference to FIG Also the parts 81 and 83 over the areas 71 and 73 are made of polycrystalline Silicon removed. The area 72 made of polycrystalline, which lies above the base contact 10 Silicon is covered with a masking lacquer layer 50. Then be through the areas 71 and 73 made of polycrystalline silicon for producing a collector contact zone 40 and an emitter zone 41 introduced (implanted) further doping. This Doping step is indicated schematically in FIG. 4 by arrows, which with B are designated.
Fig. 5 zeigt den fertigen Transistor, wobei nach Entfernung der Lackschicht 50 Aluminiumkontakte 90, 91, 92 in der dargestellten Weise auf das System aufgebracht werden, welche den Kollektor-, Basis bzw. Emitterkontakt darstellen.Fig. 5 shows the finished transistor, after removing the lacquer layer 50 aluminum contacts 90, 91, 92 applied to the system in the manner shown which represent the collector, base or emitter contact.
Da bei dem erfindungsgemäßen Verfahren die Justierung der Zonen 10, 40 und 41 durch die Maske in Form der Isolierschicht 3 mit den entsprechenden Fenstern 4, 5, 6 in einem Verfahrensschritt erfolgt, wozu nur eine Maske erforderlich ist, wird der Vorteil einer Selbstjustierung von Kollektor- und Basiskontakt sowie Emitterzone erreicht. Da letztlich die Schicht aus polykristallinem Silicium mit in Siliciumdioxid überführten Bereichen lediglich Flächenunebenheiten aufweist, welche durch die Fenster 4, 5, 6 in der Isolierschicht 3 und eine Volumenausdehnung bei der Überführung von polykristallinem Silicium in Siliciumdioxid bedingt sind, ergibt sich im Vergleich zu einer in der Planartechnik üblichen Siliciumdioxidschicht, die zur Herstellung der entsprechenden Fenster für die entsprechenden Zonen immer wieder umstrukturiert werden muß, eine ebenere Oberfläche. Es sei hier darauf verwiesen, daß die Darstellung nach Fig. 5 lediglich aus zeichnerischen Gründen zur Verdeutlichung der bei den einzelnen Prozeß schritten ablaufenden Vorgänge stark übertrieben wurde.Since in the method according to the invention, the adjustment of the zones 10, 40 and 41 through the mask in the form of the insulating layer 3 with the corresponding windows 4, 5, 6 takes place in one process step, for which only one mask is required, the advantage of a self-adjustment of the collector and base contact as well as the emitter zone achieved. Because ultimately the layer of polycrystalline silicon with in silicon dioxide transferred areas only has surface unevenness, which through the window 4, 5, 6 in the insulating layer 3 and a volume expansion during the transfer of polycrystalline silicon in silicon dioxide is a result of the comparison to a silicon dioxide layer customary in planar technology, which is used for production the corresponding windows for the corresponding zones are repeatedly restructured must be a level surface. It should be noted here that the representation according to FIG. 5 only for illustrative reasons to illustrate the in the individual process steps, processes taking place has been greatly exaggerated.
Weiterhin wird auch der Vorteil einer großen räumlichen Trennung der Kontakte 90, 91, 92 von der Einkristalloberfläche durch die Dicke der Isolierschicht 3 und der durch die Umwandlung der Schicht 7 aus polykristallinem Silicium in Siliciumdioxidbereiche erzielt.Furthermore, the advantage of a large spatial separation of the Contacts 90, 91, 92 from the single crystal surface through the thickness of the insulating layer 3 and that of the conversion of the layer 7 of polycrystalline silicon into silicon dioxide regions achieved.
Die pn-Ubergänge sind auch an der Emitterzone der Reaktion zwischen Metall und Halbleitersubstrat entzogen. Schließlich ist das gesamte Bauelement durch die erste Oberflächen-Isolierschicht sowie die umgewandelte bzw. verbleibende Schicht aus polykristallinem Silicium den Einflüssen der Umwelt entzogen.The pn junctions are also at the emitter zone of the reaction between Removed metal and semiconductor substrate. Finally the entire component is through the first surface insulating layer and the converted or remaining layer made of polycrystalline silicon withdrawn from the effects of the environment.
6 Patentansprüche 5 Figuren6 claims 5 figures
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE19762640465 DE2640465A1 (en) | 1976-09-08 | 1976-09-08 | Semiconductor substrate doped zone prodn. - applying non-doped silicon layer which is coated with two insulating layers partially removed leaving bare zones for doping |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE19762640465 DE2640465A1 (en) | 1976-09-08 | 1976-09-08 | Semiconductor substrate doped zone prodn. - applying non-doped silicon layer which is coated with two insulating layers partially removed leaving bare zones for doping |
Publications (2)
Publication Number | Publication Date |
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DE2640465A1 true DE2640465A1 (en) | 1978-03-09 |
DE2640465C2 DE2640465C2 (en) | 1989-06-15 |
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DE19762640465 Granted DE2640465A1 (en) | 1976-09-08 | 1976-09-08 | Semiconductor substrate doped zone prodn. - applying non-doped silicon layer which is coated with two insulating layers partially removed leaving bare zones for doping |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2445023A1 (en) * | 1978-12-23 | 1980-07-18 | Vlsi Technology Res Ass | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT CONTAINING POLYCRYSTALLINE SILICON |
EP0029548A1 (en) * | 1979-11-21 | 1981-06-03 | Siemens Aktiengesellschaft | Method for producing a bipolar transistor |
EP0029887A1 (en) * | 1979-12-03 | 1981-06-10 | International Business Machines Corporation | Process for producing a vertical PNP transistor and transistor so produced |
EP0034910B1 (en) * | 1980-02-18 | 1985-01-09 | VLSI Technology Research Association | A method of manufacturing a semiconductor device, and a device so manufactured |
EP0477995A1 (en) * | 1985-04-01 | 1992-04-01 | Fairchild Semiconductor Corporation | Process for forming CMOS and bipolar devices on the same substrate |
US5340762A (en) * | 1985-04-01 | 1994-08-23 | Fairchild Semiconductor Corporation | Method of making small contactless RAM cell |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2225374A1 (en) * | 1971-05-28 | 1973-06-20 | Fujitsu Ltd | Semiconductor device and process for its production |
-
1976
- 1976-09-08 DE DE19762640465 patent/DE2640465A1/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2225374A1 (en) * | 1971-05-28 | 1973-06-20 | Fujitsu Ltd | Semiconductor device and process for its production |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2445023A1 (en) * | 1978-12-23 | 1980-07-18 | Vlsi Technology Res Ass | METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT CONTAINING POLYCRYSTALLINE SILICON |
EP0029548A1 (en) * | 1979-11-21 | 1981-06-03 | Siemens Aktiengesellschaft | Method for producing a bipolar transistor |
EP0029887A1 (en) * | 1979-12-03 | 1981-06-10 | International Business Machines Corporation | Process for producing a vertical PNP transistor and transistor so produced |
EP0034910B1 (en) * | 1980-02-18 | 1985-01-09 | VLSI Technology Research Association | A method of manufacturing a semiconductor device, and a device so manufactured |
EP0477995A1 (en) * | 1985-04-01 | 1992-04-01 | Fairchild Semiconductor Corporation | Process for forming CMOS and bipolar devices on the same substrate |
US5340762A (en) * | 1985-04-01 | 1994-08-23 | Fairchild Semiconductor Corporation | Method of making small contactless RAM cell |
Also Published As
Publication number | Publication date |
---|---|
DE2640465C2 (en) | 1989-06-15 |
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