DE2617482A1 - Verfahren zur dielektrischen isolation integrierter halbleiteranordnungen - Google Patents

Verfahren zur dielektrischen isolation integrierter halbleiteranordnungen

Info

Publication number
DE2617482A1
DE2617482A1 DE19762617482 DE2617482A DE2617482A1 DE 2617482 A1 DE2617482 A1 DE 2617482A1 DE 19762617482 DE19762617482 DE 19762617482 DE 2617482 A DE2617482 A DE 2617482A DE 2617482 A1 DE2617482 A1 DE 2617482A1
Authority
DE
Germany
Prior art keywords
zones
isolation
depressions
epitaxial layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19762617482
Other languages
German (de)
English (en)
Inventor
Jacob Riseman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2617482A1 publication Critical patent/DE2617482A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Element Separation (AREA)
DE19762617482 1975-05-30 1976-04-22 Verfahren zur dielektrischen isolation integrierter halbleiteranordnungen Withdrawn DE2617482A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/582,336 US3972754A (en) 1975-05-30 1975-05-30 Method for forming dielectric isolation in integrated circuits

Publications (1)

Publication Number Publication Date
DE2617482A1 true DE2617482A1 (de) 1976-12-16

Family

ID=24328734

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762617482 Withdrawn DE2617482A1 (de) 1975-05-30 1976-04-22 Verfahren zur dielektrischen isolation integrierter halbleiteranordnungen

Country Status (7)

Country Link
US (1) US3972754A (https=)
JP (1) JPS51147189A (https=)
CA (1) CA1048658A (https=)
DE (1) DE2617482A1 (https=)
FR (1) FR2312857A1 (https=)
GB (1) GB1516264A (https=)
IT (1) IT1063602B (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4066485A (en) * 1977-01-21 1978-01-03 Rca Corporation Method of fabricating a semiconductor device
US4104090A (en) * 1977-02-24 1978-08-01 International Business Machines Corporation Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation
US4111720A (en) * 1977-03-31 1978-09-05 International Business Machines Corporation Method for forming a non-epitaxial bipolar integrated circuit
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4180416A (en) * 1978-09-27 1979-12-25 International Business Machines Corporation Thermal migration-porous silicon technique for forming deep dielectric isolation
US4322882A (en) * 1980-02-04 1982-04-06 Fairchild Camera & Instrument Corp. Method for making an integrated injection logic structure including a self-aligned base contact
FR2512999A1 (fr) * 1981-09-14 1983-03-18 Radiotechnique Compelec Dispositif semiconducteur formant memoire morte programmable a transistors
FR2538615A1 (fr) * 1982-12-22 1984-06-29 Trt Telecom Radio Electr Procede de fabrication de circuits integres bipolaires a isolation dielectrique et circuits integres ainsi obtenus
FR2543740B1 (fr) * 1983-03-28 1986-05-09 Trt Telecom Radio Electr Procede de realisation de transistors par integration monolithique en technologie isoplanar et circuits integres ainsi obtenus
JPS6088468A (ja) * 1983-10-13 1985-05-18 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 半導体集積装置の製造方法
US4771328A (en) * 1983-10-13 1988-09-13 International Business Machine Corporation Semiconductor device and process
GB2238658B (en) * 1989-11-23 1993-02-17 Stc Plc Improvements in integrated circuits
US20090127659A1 (en) * 2007-11-15 2009-05-21 Zia Alan Shafi Bipolar junction transistor with a low collector resistance and method of forming the bipolar junction transistor in a CMOS process flow

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3379584A (en) * 1964-09-04 1968-04-23 Texas Instruments Inc Semiconductor wafer with at least one epitaxial layer and methods of making same
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3481801A (en) * 1966-10-10 1969-12-02 Frances Hugle Isolation technique for integrated circuits
US3648125A (en) * 1971-02-02 1972-03-07 Fairchild Camera Instr Co Method of fabricating integrated circuits with oxidized isolation and the resulting structure
US3796613A (en) * 1971-06-18 1974-03-12 Ibm Method of forming dielectric isolation for high density pedestal semiconductor devices
US3861968A (en) * 1972-06-19 1975-01-21 Ibm Method of fabricating integrated circuit device structure with complementary elements utilizing selective thermal oxidation and selective epitaxial deposition
JPS49126286A (https=) * 1973-04-04 1974-12-03

Also Published As

Publication number Publication date
JPS51147189A (en) 1976-12-17
IT1063602B (it) 1985-02-11
GB1516264A (en) 1978-06-28
FR2312857A1 (fr) 1976-12-24
CA1048658A (en) 1979-02-13
US3972754A (en) 1976-08-03
FR2312857B1 (https=) 1978-11-17

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee