DE2617102C2 - Verfahren zum Abgleichen eines Halbleiterbauelementes - Google Patents

Verfahren zum Abgleichen eines Halbleiterbauelementes

Info

Publication number
DE2617102C2
DE2617102C2 DE2617102A DE2617102A DE2617102C2 DE 2617102 C2 DE2617102 C2 DE 2617102C2 DE 2617102 A DE2617102 A DE 2617102A DE 2617102 A DE2617102 A DE 2617102A DE 2617102 C2 DE2617102 C2 DE 2617102C2
Authority
DE
Germany
Prior art keywords
balancing
short
circuit bridge
semiconductor component
pole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2617102A
Other languages
German (de)
English (en)
Other versions
DE2617102A1 (de
Inventor
Harald 7800 Freiburg Schilling
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE2617102A priority Critical patent/DE2617102C2/de
Priority to JP3123477A priority patent/JPS52127187A/ja
Priority to GB7714820A priority patent/GB1542612A/en
Priority to IT22446/77A priority patent/IT1077905B/it
Priority to FR7711428A priority patent/FR2348576A1/fr
Publication of DE2617102A1 publication Critical patent/DE2617102A1/de
Application granted granted Critical
Publication of DE2617102C2 publication Critical patent/DE2617102C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE2617102A 1976-04-17 1976-04-17 Verfahren zum Abgleichen eines Halbleiterbauelementes Expired DE2617102C2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE2617102A DE2617102C2 (de) 1976-04-17 1976-04-17 Verfahren zum Abgleichen eines Halbleiterbauelementes
JP3123477A JPS52127187A (en) 1976-04-17 1977-03-23 Method of adjusting semiconductor device
GB7714820A GB1542612A (en) 1976-04-17 1977-04-07 Method of trimming semiconductor circuits
IT22446/77A IT1077905B (it) 1976-04-17 1977-04-14 Procedimento per la regolazione di dispositivi semiconduttori
FR7711428A FR2348576A1 (fr) 1976-04-17 1977-04-15 Methode pour l'ajustement de dispositifs a semi-conducteurs

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2617102A DE2617102C2 (de) 1976-04-17 1976-04-17 Verfahren zum Abgleichen eines Halbleiterbauelementes

Publications (2)

Publication Number Publication Date
DE2617102A1 DE2617102A1 (de) 1977-10-27
DE2617102C2 true DE2617102C2 (de) 1984-05-30

Family

ID=5975716

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2617102A Expired DE2617102C2 (de) 1976-04-17 1976-04-17 Verfahren zum Abgleichen eines Halbleiterbauelementes

Country Status (5)

Country Link
JP (1) JPS52127187A (enExample)
DE (1) DE2617102C2 (enExample)
FR (1) FR2348576A1 (enExample)
GB (1) GB1542612A (enExample)
IT (1) IT1077905B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3122984A1 (de) * 1981-06-10 1983-01-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zur kennzeichnung von halbleiterchips und kennzeichenbarer helbleiterchip
FR2582150B1 (fr) * 1985-05-15 1987-10-23 Cahen Olivier Dispositif de compensation des ecarts de tension de seuil des transistors a effet de champ des circuits integres analogiques

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2256688B2 (de) * 1972-11-18 1976-05-06 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zum auftrennen von leiterbahnen auf integrierten schaltkreisen

Also Published As

Publication number Publication date
FR2348576A1 (fr) 1977-11-10
FR2348576B1 (enExample) 1983-10-28
GB1542612A (en) 1979-03-21
DE2617102A1 (de) 1977-10-27
JPS52127187A (en) 1977-10-25
IT1077905B (it) 1985-05-04

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Legal Events

Date Code Title Description
8101 Request for examination as to novelty
8110 Request for examination paragraph 44
8181 Inventor (new situation)

Free format text: SCHILLING, HARALD, 7800 FREIBURG, DE

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee