IT1077905B - Procedimento per la regolazione di dispositivi semiconduttori - Google Patents
Procedimento per la regolazione di dispositivi semiconduttoriInfo
- Publication number
- IT1077905B IT1077905B IT22446/77A IT2244677A IT1077905B IT 1077905 B IT1077905 B IT 1077905B IT 22446/77 A IT22446/77 A IT 22446/77A IT 2244677 A IT2244677 A IT 2244677A IT 1077905 B IT1077905 B IT 1077905B
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- adjustment
- semiconductive devices
- semiconductive
- devices
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2617102A DE2617102C2 (de) | 1976-04-17 | 1976-04-17 | Verfahren zum Abgleichen eines Halbleiterbauelementes |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT1077905B true IT1077905B (it) | 1985-05-04 |
Family
ID=5975716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT22446/77A IT1077905B (it) | 1976-04-17 | 1977-04-14 | Procedimento per la regolazione di dispositivi semiconduttori |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS52127187A (enExample) |
| DE (1) | DE2617102C2 (enExample) |
| FR (1) | FR2348576A1 (enExample) |
| GB (1) | GB1542612A (enExample) |
| IT (1) | IT1077905B (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3122984A1 (de) * | 1981-06-10 | 1983-01-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur kennzeichnung von halbleiterchips und kennzeichenbarer helbleiterchip |
| FR2582150B1 (fr) * | 1985-05-15 | 1987-10-23 | Cahen Olivier | Dispositif de compensation des ecarts de tension de seuil des transistors a effet de champ des circuits integres analogiques |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2256688B2 (de) * | 1972-11-18 | 1976-05-06 | Robert Bosch Gmbh, 7000 Stuttgart | Verfahren zum auftrennen von leiterbahnen auf integrierten schaltkreisen |
-
1976
- 1976-04-17 DE DE2617102A patent/DE2617102C2/de not_active Expired
-
1977
- 1977-03-23 JP JP3123477A patent/JPS52127187A/ja active Pending
- 1977-04-07 GB GB7714820A patent/GB1542612A/en not_active Expired
- 1977-04-14 IT IT22446/77A patent/IT1077905B/it active
- 1977-04-15 FR FR7711428A patent/FR2348576A1/fr active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| FR2348576A1 (fr) | 1977-11-10 |
| FR2348576B1 (enExample) | 1983-10-28 |
| GB1542612A (en) | 1979-03-21 |
| DE2617102C2 (de) | 1984-05-30 |
| DE2617102A1 (de) | 1977-10-27 |
| JPS52127187A (en) | 1977-10-25 |
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