JPS52127187A - Method of adjusting semiconductor device - Google Patents

Method of adjusting semiconductor device

Info

Publication number
JPS52127187A
JPS52127187A JP3123477A JP3123477A JPS52127187A JP S52127187 A JPS52127187 A JP S52127187A JP 3123477 A JP3123477 A JP 3123477A JP 3123477 A JP3123477 A JP 3123477A JP S52127187 A JPS52127187 A JP S52127187A
Authority
JP
Japan
Prior art keywords
semiconductor device
adjusting semiconductor
adjusting
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3123477A
Other languages
English (en)
Japanese (ja)
Inventor
Shiyurinku Hararuto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of JPS52127187A publication Critical patent/JPS52127187A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP3123477A 1976-04-17 1977-03-23 Method of adjusting semiconductor device Pending JPS52127187A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2617102A DE2617102C2 (de) 1976-04-17 1976-04-17 Verfahren zum Abgleichen eines Halbleiterbauelementes

Publications (1)

Publication Number Publication Date
JPS52127187A true JPS52127187A (en) 1977-10-25

Family

ID=5975716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3123477A Pending JPS52127187A (en) 1976-04-17 1977-03-23 Method of adjusting semiconductor device

Country Status (5)

Country Link
JP (1) JPS52127187A (enExample)
DE (1) DE2617102C2 (enExample)
FR (1) FR2348576A1 (enExample)
GB (1) GB1542612A (enExample)
IT (1) IT1077905B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3122984A1 (de) * 1981-06-10 1983-01-27 Siemens AG, 1000 Berlin und 8000 München Verfahren zur kennzeichnung von halbleiterchips und kennzeichenbarer helbleiterchip
FR2582150B1 (fr) * 1985-05-15 1987-10-23 Cahen Olivier Dispositif de compensation des ecarts de tension de seuil des transistors a effet de champ des circuits integres analogiques

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2256688B2 (de) * 1972-11-18 1976-05-06 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zum auftrennen von leiterbahnen auf integrierten schaltkreisen

Also Published As

Publication number Publication date
FR2348576A1 (fr) 1977-11-10
FR2348576B1 (enExample) 1983-10-28
GB1542612A (en) 1979-03-21
DE2617102C2 (de) 1984-05-30
DE2617102A1 (de) 1977-10-27
IT1077905B (it) 1985-05-04

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