DE2538264C3 - Verfahren zur Herstellung einer planaren integrierten Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer planaren integrierten Halbleiteranordnung

Info

Publication number
DE2538264C3
DE2538264C3 DE2538264A DE2538264A DE2538264C3 DE 2538264 C3 DE2538264 C3 DE 2538264C3 DE 2538264 A DE2538264 A DE 2538264A DE 2538264 A DE2538264 A DE 2538264A DE 2538264 C3 DE2538264 C3 DE 2538264C3
Authority
DE
Germany
Prior art keywords
layer
insulating layer
window
semiconductor wafer
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2538264A
Other languages
German (de)
English (en)
Other versions
DE2538264A1 (de
DE2538264B2 (de
Inventor
Jean Pierre Epron Rioult
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2538264A1 publication Critical patent/DE2538264A1/de
Publication of DE2538264B2 publication Critical patent/DE2538264B2/de
Application granted granted Critical
Publication of DE2538264C3 publication Critical patent/DE2538264C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Weting (AREA)
DE2538264A 1974-09-10 1975-08-28 Verfahren zur Herstellung einer planaren integrierten Halbleiteranordnung Expired DE2538264C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7430623A FR2284981A1 (fr) 1974-09-10 1974-09-10 Procede d'obtention d'un circuit integre semiconducteur

Publications (3)

Publication Number Publication Date
DE2538264A1 DE2538264A1 (de) 1976-03-18
DE2538264B2 DE2538264B2 (de) 1981-04-30
DE2538264C3 true DE2538264C3 (de) 1982-01-14

Family

ID=9142928

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2538264A Expired DE2538264C3 (de) 1974-09-10 1975-08-28 Verfahren zur Herstellung einer planaren integrierten Halbleiteranordnung

Country Status (10)

Country Link
JP (1) JPS5744017B2 (enExample)
AT (1) AT359562B (enExample)
CA (1) CA1035470A (enExample)
CH (1) CH591163A5 (enExample)
DE (1) DE2538264C3 (enExample)
FR (1) FR2284981A1 (enExample)
GB (1) GB1518988A (enExample)
IT (1) IT1042339B (enExample)
NL (1) NL7510427A (enExample)
SE (1) SE415421B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5496775A (en) * 1978-01-17 1979-07-31 Hitachi Ltd Method of forming circuit
FR2535525A1 (fr) * 1982-10-29 1984-05-04 Western Electric Co Procede de fabrication de circuits integres comportant des couches isolantes minces
JPH053192A (ja) * 1991-10-25 1993-01-08 Matsushita Electron Corp 半導体集積回路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979768A (en) * 1966-03-23 1976-09-07 Hitachi, Ltd. Semiconductor element having surface coating comprising silicon nitride and silicon oxide films
FR1536321A (fr) * 1966-06-30 1968-08-10 Texas Instruments Inc Contacts ohmiques pour des dispositifs à semi-conducteurs
FR1531852A (fr) * 1966-07-15 1968-07-05 Itt Procédé de masquage de la surface d'un support
US3474310A (en) * 1967-02-03 1969-10-21 Hitachi Ltd Semiconductor device having a sulfurtreated silicon compound thereon and a method of making the same
US3442012A (en) * 1967-08-03 1969-05-06 Teledyne Inc Method of forming a flip-chip integrated circuit
DE2059116C3 (de) * 1970-12-01 1974-11-21 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung eines Halbleiterbauelementes
GB1363815A (en) * 1971-12-06 1974-08-21 Tektronix Inc Semiconductor device and method of producing same
JPS4960870A (enExample) * 1972-10-16 1974-06-13

Also Published As

Publication number Publication date
FR2284981B1 (enExample) 1978-11-24
DE2538264A1 (de) 1976-03-18
FR2284981A1 (fr) 1976-04-09
AU8461075A (en) 1977-03-17
AT359562B (de) 1980-11-25
DE2538264B2 (de) 1981-04-30
CA1035470A (en) 1978-07-25
IT1042339B (it) 1980-01-30
NL7510427A (nl) 1976-03-12
CH591163A5 (enExample) 1977-09-15
ATA692075A (de) 1980-04-15
SE415421B (sv) 1980-09-29
JPS5153491A (enExample) 1976-05-11
JPS5744017B2 (enExample) 1982-09-18
GB1518988A (en) 1978-07-26
SE7509970L (sv) 1976-03-11

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Legal Events

Date Code Title Description
OD Request for examination
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee