DE2500207A1 - Integrierte halbleiteranordnung und verfahren zu ihrer herstellung - Google Patents

Integrierte halbleiteranordnung und verfahren zu ihrer herstellung

Info

Publication number
DE2500207A1
DE2500207A1 DE19752500207 DE2500207A DE2500207A1 DE 2500207 A1 DE2500207 A1 DE 2500207A1 DE 19752500207 DE19752500207 DE 19752500207 DE 2500207 A DE2500207 A DE 2500207A DE 2500207 A1 DE2500207 A1 DE 2500207A1
Authority
DE
Germany
Prior art keywords
semiconductor
area
channel
covered
semiconductor material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19752500207
Other languages
German (de)
English (en)
Inventor
Donald Keith Roberson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE2500207A1 publication Critical patent/DE2500207A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/115—Orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19752500207 1974-01-03 1975-01-03 Integrierte halbleiteranordnung und verfahren zu ihrer herstellung Pending DE2500207A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US430434A US3913124A (en) 1974-01-03 1974-01-03 Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor

Publications (1)

Publication Number Publication Date
DE2500207A1 true DE2500207A1 (de) 1975-07-24

Family

ID=23707550

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752500207 Pending DE2500207A1 (de) 1974-01-03 1975-01-03 Integrierte halbleiteranordnung und verfahren zu ihrer herstellung

Country Status (5)

Country Link
US (1) US3913124A (en, 2012)
JP (1) JPS5245196B2 (en, 2012)
DE (1) DE2500207A1 (en, 2012)
FR (1) FR2257148B1 (en, 2012)
GB (1) GB1460124A (en, 2012)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4026736A (en) * 1974-01-03 1977-05-31 Motorola, Inc. Integrated semiconductor structure with combined dielectric and PN junction isolation including fabrication method therefor
GB1534896A (en) * 1975-05-19 1978-12-06 Itt Direct metal contact to buried layer
JPS5534442A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
US4255207A (en) * 1979-04-09 1981-03-10 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
US4670769A (en) * 1979-04-09 1987-06-02 Harris Corporation Fabrication of isolated regions for use in self-aligning device process utilizing selective oxidation
US4252581A (en) * 1979-10-01 1981-02-24 International Business Machines Corporation Selective epitaxy method for making filamentary pedestal transistor
US4476623A (en) * 1979-10-22 1984-10-16 International Business Machines Corporation Method of fabricating a bipolar dynamic memory cell
FR2480501A1 (fr) * 1980-04-14 1981-10-16 Thomson Csf Dispositif semi-conducteur a grille profonde accessible par la surface et procede de fabrication
FR2498812A1 (fr) * 1981-01-27 1982-07-30 Thomson Csf Structure de transistors dans un circuit integre et son procede de fabrication
US4503451A (en) * 1982-07-30 1985-03-05 Motorola, Inc. Low resistance buried power bus for integrated circuits
JPS59165455A (ja) * 1983-03-10 1984-09-18 Toshiba Corp 半導体装置
US4982262A (en) * 1985-01-15 1991-01-01 At&T Bell Laboratories Inverted groove isolation technique for merging dielectrically isolated semiconductor devices
US4933733A (en) * 1985-06-03 1990-06-12 Advanced Micro Devices, Inc. Slot collector transistor
JPH0719838B2 (ja) * 1985-07-19 1995-03-06 松下電器産業株式会社 半導体装置およびその製造方法
EP0219641B1 (de) * 1985-09-13 1991-01-09 Siemens Aktiengesellschaft Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
US4717681A (en) * 1986-05-19 1988-01-05 Texas Instruments Incorporated Method of making a heterojunction bipolar transistor with SIPOS
EP0256315B1 (de) * 1986-08-13 1992-01-29 Siemens Aktiengesellschaft Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
JP2535519B2 (ja) * 1986-11-14 1996-09-18 富士通株式会社 半導体集積回路装置とその製造方法
US4745087A (en) * 1987-01-13 1988-05-17 Advanced Micro Devices, Inc. Method of making fully self-aligned bipolar transistor involving a polysilicon collector contact formed in a slot with an oxide sidewall
US5003365A (en) * 1988-06-09 1991-03-26 Texas Instruments Incorporated Bipolar transistor with a sidewall-diffused subcollector
GB8926415D0 (en) * 1989-11-18 1990-01-10 Lsi Logic Europ Silicon bipolar junction transistors
JP2526786B2 (ja) * 1993-05-22 1996-08-21 日本電気株式会社 半導体装置及びその製造方法
US6232649B1 (en) * 1994-12-12 2001-05-15 Hyundai Electronics America Bipolar silicon-on-insulator structure and process

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1095413A (en, 2012) * 1964-12-24
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3471922A (en) * 1966-06-02 1969-10-14 Raytheon Co Monolithic integrated circuitry with dielectric isolated functional regions
US3791882A (en) * 1966-08-31 1974-02-12 K Ogiue Method of manufacturing semiconductor devices utilizing simultaneous deposition of monocrystalline and polycrystalline regions
FR1527898A (fr) * 1967-03-16 1968-06-07 Radiotechnique Coprim Rtc Agencement de dispositifs semi-conducteurs portés par un support commun et son procédé de fabrication
DE1933731C3 (de) * 1968-07-05 1982-03-25 Honeywell Information Systems Italia S.p.A., Caluso, Torino Verfahren zum Herstellen einer integrierten Halbleiterschaltung
US3768150A (en) * 1970-02-13 1973-10-30 B Sloan Integrated circuit process utilizing orientation dependent silicon etch
US3796613A (en) * 1971-06-18 1974-03-12 Ibm Method of forming dielectric isolation for high density pedestal semiconductor devices
JPS5120267B2 (en, 2012) * 1972-05-13 1976-06-23

Also Published As

Publication number Publication date
GB1460124A (en) 1976-12-31
FR2257148B1 (en, 2012) 1976-12-31
JPS50102278A (en, 2012) 1975-08-13
US3913124A (en) 1975-10-14
JPS5245196B2 (en, 2012) 1977-11-14
FR2257148A1 (en, 2012) 1975-08-01

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