DE2445480A1 - Verfahren zur herstellung eines leistungstransistors - Google Patents

Verfahren zur herstellung eines leistungstransistors

Info

Publication number
DE2445480A1
DE2445480A1 DE19742445480 DE2445480A DE2445480A1 DE 2445480 A1 DE2445480 A1 DE 2445480A1 DE 19742445480 DE19742445480 DE 19742445480 DE 2445480 A DE2445480 A DE 2445480A DE 2445480 A1 DE2445480 A1 DE 2445480A1
Authority
DE
Germany
Prior art keywords
zone
emitter
base
base zone
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19742445480
Other languages
German (de)
English (en)
Inventor
Manfred Dipl Phys Dahmen
Anneliese Ritzhaupt
Manfred Dipl Phys Zurheide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM Deutschland GmbH
Original Assignee
IBM Deutschland GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IBM Deutschland GmbH filed Critical IBM Deutschland GmbH
Priority to DE19742445480 priority Critical patent/DE2445480A1/de
Priority to US05/589,276 priority patent/US3970487A/en
Priority to GB32784/75A priority patent/GB1501894A/en
Priority to FR7526330A priority patent/FR2286503A1/fr
Priority to JP50103108A priority patent/JPS5151289A/ja
Publication of DE2445480A1 publication Critical patent/DE2445480A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H10P10/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H10P95/00—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/139—Schottky barrier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions

Landscapes

  • Bipolar Transistors (AREA)
DE19742445480 1974-09-24 1974-09-24 Verfahren zur herstellung eines leistungstransistors Withdrawn DE2445480A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE19742445480 DE2445480A1 (de) 1974-09-24 1974-09-24 Verfahren zur herstellung eines leistungstransistors
US05/589,276 US3970487A (en) 1974-09-24 1975-06-16 Method of manufacturing a power transistor
GB32784/75A GB1501894A (en) 1974-09-24 1975-08-06 Method of manufacturing a power transistor
FR7526330A FR2286503A1 (fr) 1974-09-24 1975-08-19 Procede de fabrication d'un transistor de puissance
JP50103108A JPS5151289A (enExample) 1974-09-24 1975-08-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742445480 DE2445480A1 (de) 1974-09-24 1974-09-24 Verfahren zur herstellung eines leistungstransistors

Publications (1)

Publication Number Publication Date
DE2445480A1 true DE2445480A1 (de) 1976-04-01

Family

ID=5926552

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19742445480 Withdrawn DE2445480A1 (de) 1974-09-24 1974-09-24 Verfahren zur herstellung eines leistungstransistors

Country Status (5)

Country Link
US (1) US3970487A (enExample)
JP (1) JPS5151289A (enExample)
DE (1) DE2445480A1 (enExample)
FR (1) FR2286503A1 (enExample)
GB (1) GB1501894A (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL184589C (nl) * 1979-07-13 1989-09-01 Philips Nv Halfgeleiderinrichting voor het opwekken van een elektronenbundel en werkwijze voor het vervaardigen van een dergelijke halfgeleiderinrichting.
US4954455A (en) * 1984-12-18 1990-09-04 Advanced Micro Devices Semiconductor memory device having protection against alpha strike induced errors
IT1298516B1 (it) * 1998-01-30 2000-01-12 Sgs Thomson Microelectronics Dispositivo elettronico di potenza integrato su un materiale semiconduttore e relativo processo di fabricazione

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6502122A (enExample) * 1964-02-24 1965-08-25
FR1488176A (fr) * 1965-08-02 1967-07-07 Gen Electric Perfectionnements aux dispositifs à semiconducteurs
US3678573A (en) * 1970-03-10 1972-07-25 Westinghouse Electric Corp Self-aligned gate field effect transistor and method of preparing
JPS4814638B1 (enExample) * 1970-04-03 1973-05-09
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
US3806361A (en) * 1972-01-24 1974-04-23 Motorola Inc Method of making electrical contacts for and passivating a semiconductor device

Also Published As

Publication number Publication date
JPS5151289A (enExample) 1976-05-06
GB1501894A (en) 1978-02-22
FR2286503B1 (enExample) 1978-04-07
US3970487A (en) 1976-07-20
FR2286503A1 (fr) 1976-04-23

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee