DE2440481C3 - Verfahren zum Herstellen von Dünnschicht-Leiterzügen auf einem elektrisch isolierenden Träger - Google Patents

Verfahren zum Herstellen von Dünnschicht-Leiterzügen auf einem elektrisch isolierenden Träger

Info

Publication number
DE2440481C3
DE2440481C3 DE2440481A DE2440481A DE2440481C3 DE 2440481 C3 DE2440481 C3 DE 2440481C3 DE 2440481 A DE2440481 A DE 2440481A DE 2440481 A DE2440481 A DE 2440481A DE 2440481 C3 DE2440481 C3 DE 2440481C3
Authority
DE
Germany
Prior art keywords
layer
conductor
noble metal
conductor tracks
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2440481A
Other languages
German (de)
English (en)
Other versions
DE2440481A1 (de
DE2440481B2 (de
Inventor
Herbert Carl Milton Cook
Paul Alden Burlington Farrar
Robert Lee Essex Junction Hallen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2440481A1 publication Critical patent/DE2440481A1/de
Publication of DE2440481B2 publication Critical patent/DE2440481B2/de
Application granted granted Critical
Publication of DE2440481C3 publication Critical patent/DE2440481C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H10P95/00—
    • H10W20/425—
    • H10W20/4432—
    • H10W72/012—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H10W72/251—
    • H10W72/923—
    • H10W72/952—

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)
  • Physical Vapour Deposition (AREA)
DE2440481A 1973-10-12 1974-08-23 Verfahren zum Herstellen von Dünnschicht-Leiterzügen auf einem elektrisch isolierenden Träger Expired DE2440481C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US406125A US3881884A (en) 1973-10-12 1973-10-12 Method for the formation of corrosion resistant electronic interconnections

Publications (3)

Publication Number Publication Date
DE2440481A1 DE2440481A1 (de) 1975-04-24
DE2440481B2 DE2440481B2 (de) 1977-12-01
DE2440481C3 true DE2440481C3 (de) 1978-08-03

Family

ID=23606638

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2440481A Expired DE2440481C3 (de) 1973-10-12 1974-08-23 Verfahren zum Herstellen von Dünnschicht-Leiterzügen auf einem elektrisch isolierenden Träger

Country Status (11)

Country Link
US (1) US3881884A (OSRAM)
JP (1) JPS5310430B2 (OSRAM)
BR (1) BR7408490D0 (OSRAM)
CA (1) CA1023876A (OSRAM)
CH (1) CH569363A5 (OSRAM)
DE (1) DE2440481C3 (OSRAM)
FR (1) FR2247820B1 (OSRAM)
GB (1) GB1448034A (OSRAM)
IT (1) IT1020141B (OSRAM)
NL (1) NL7413310A (OSRAM)
SE (1) SE401291B (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319264A (en) 1979-12-17 1982-03-09 International Business Machines Corporation Nickel-gold-nickel conductors for solid state devices

Families Citing this family (38)

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JPS556833A (en) * 1978-06-29 1980-01-18 Nippon Mektron Kk Cirucit board and method of manufacturing same
DE2834221C3 (de) * 1978-08-04 1981-04-30 Preh Elektrofeinmechanische Werke Jakob Preh Nachf. GmbH & Co, 8740 Bad Neustadt Verfahren zur Herstellung von Dünnschichtleiterbahnen
JPS5534414A (en) * 1978-09-01 1980-03-11 Sumitomo Bakelite Co Method of manufacturing printed circuit board
US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4360142A (en) * 1979-06-29 1982-11-23 International Business Machines Corporation Method of forming a solder interconnection capable of sustained high power levels between a semiconductor device and a supporting substrate
US4290079A (en) * 1979-06-29 1981-09-15 International Business Machines Corporation Improved solder interconnection between a semiconductor device and a supporting substrate
US4335506A (en) * 1980-08-04 1982-06-22 International Business Machines Corporation Method of forming aluminum/copper alloy conductors
JPS57141942A (en) * 1981-02-27 1982-09-02 Fuji Electric Corp Res & Dev Ltd Formation of bump electrode
DE3107857C2 (de) * 1981-03-02 1984-08-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Dünnfilmschaltungen mit sehr gut lötbaren Leiterbahnschichtsystemen
DE3107943A1 (de) * 1981-03-02 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von loetbaren und temperfaehigen edelmetallfreien duennschichtleiterbahnen
US4505029A (en) * 1981-03-23 1985-03-19 General Electric Company Semiconductor device with built-up low resistance contact
US4386116A (en) * 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
US4396900A (en) * 1982-03-08 1983-08-02 The United States Of America As Represented By The Secretary Of The Navy Thin film microstrip circuits
DE3343362A1 (de) * 1983-11-30 1985-06-05 Siemens AG, 1000 Berlin und 8000 München Verfahren zur galvanischen herstellung metallischer, hoeckerartiger anschlusskontakte
US4606788A (en) * 1984-04-12 1986-08-19 Moran Peter L Methods of and apparatus for forming conductive patterns on a substrate
US4851895A (en) * 1985-05-06 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Metallization for integrated devices
US4725877A (en) * 1986-04-11 1988-02-16 American Telephone And Telegraph Company, At&T Bell Laboratories Metallized semiconductor device including an interface layer
US4711791A (en) * 1986-08-04 1987-12-08 The Boc Group, Inc. Method of making a flexible microcircuit
JP2500523B2 (ja) * 1990-12-28 1996-05-29 日本電装株式会社 基板および基板の製造方法
GB2255672B (en) * 1991-05-10 1994-11-30 Northern Telecom Ltd Opto-electronic components
US5288541A (en) * 1991-10-17 1994-02-22 International Business Machines Corporation Method for metallizing through holes in thin film substrates, and resulting devices
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
JP2003023239A (ja) * 2001-07-05 2003-01-24 Sumitomo Electric Ind Ltd 回路基板とその製造方法及び高出力モジュール
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
KR100396787B1 (ko) * 2001-11-13 2003-09-02 엘지전자 주식회사 반도체 패키지용 인쇄회로기판의 와이어 본딩패드 형성방법
US20030183943A1 (en) * 2002-03-28 2003-10-02 Swan Johanna M. Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6908845B2 (en) * 2002-03-28 2005-06-21 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
US6848177B2 (en) * 2002-03-28 2005-02-01 Intel Corporation Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme
JP3962039B2 (ja) * 2004-06-17 2007-08-22 日東電工株式会社 配線回路形成用基板、配線回路基板および金属薄層の形成方法
US7339267B2 (en) * 2005-05-26 2008-03-04 Freescale Semiconductor, Inc. Semiconductor package and method for forming the same
US10373930B2 (en) * 2012-08-10 2019-08-06 Cyntec Co., Ltd Package structure and the method to fabricate thereof
JP6563366B2 (ja) * 2016-06-13 2019-08-21 新光電気工業株式会社 配線基板及びその製造方法
CN113133217A (zh) * 2020-01-15 2021-07-16 鹏鼎控股(深圳)股份有限公司 线路板的制备方法
KR20230093308A (ko) * 2020-11-27 2023-06-27 교세라 가부시키가이샤 배선 기판

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2724663A (en) * 1952-10-23 1955-11-22 Bell Telephone Labor Inc Plural metal vapor coating
US3458925A (en) * 1966-01-20 1969-08-05 Ibm Method of forming solder mounds on substrates
US3677843A (en) * 1970-02-02 1972-07-18 Sylvania Electric Prod Method for fabricating multilayer magnetic devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4319264A (en) 1979-12-17 1982-03-09 International Business Machines Corporation Nickel-gold-nickel conductors for solid state devices

Also Published As

Publication number Publication date
BR7408490D0 (pt) 1975-07-29
CH569363A5 (OSRAM) 1975-11-14
SE7412333L (OSRAM) 1975-04-14
IT1020141B (it) 1977-12-20
NL7413310A (nl) 1975-04-15
JPS5068082A (OSRAM) 1975-06-07
DE2440481A1 (de) 1975-04-24
US3881884A (en) 1975-05-06
SE401291B (sv) 1978-04-24
CA1023876A (en) 1978-01-03
FR2247820A1 (OSRAM) 1975-05-09
GB1448034A (en) 1976-09-02
FR2247820B1 (OSRAM) 1976-10-22
DE2440481B2 (de) 1977-12-01
JPS5310430B2 (OSRAM) 1978-04-13

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee