DE3638799C2 - - Google Patents

Info

Publication number
DE3638799C2
DE3638799C2 DE3638799A DE3638799A DE3638799C2 DE 3638799 C2 DE3638799 C2 DE 3638799C2 DE 3638799 A DE3638799 A DE 3638799A DE 3638799 A DE3638799 A DE 3638799A DE 3638799 C2 DE3638799 C2 DE 3638799C2
Authority
DE
Germany
Prior art keywords
film
substrate
silicon
conductive film
electrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE3638799A
Other languages
German (de)
English (en)
Other versions
DE3638799A1 (de
Inventor
Peter L. King County Wash. Us Young
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OPTICAL MATERIALS Inc MERCER ISLAND WASH US
Original Assignee
OPTICAL MATERIALS Inc MERCER ISLAND WASH US
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by OPTICAL MATERIALS Inc MERCER ISLAND WASH US filed Critical OPTICAL MATERIALS Inc MERCER ISLAND WASH US
Publication of DE3638799A1 publication Critical patent/DE3638799A1/de
Application granted granted Critical
Publication of DE3638799C2 publication Critical patent/DE3638799C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0293—Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/067—Manufacture or treatment of conductive parts of the interconnections by modifying the pattern of conductive parts
    • H10W20/068—Manufacture or treatment of conductive parts of the interconnections by modifying the pattern of conductive parts by using a laser, e.g. laser cutting or laser direct writing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/491—Antifuses, i.e. interconnections changeable from non-conductive to conductive
    • H10W20/492—Antifuses, i.e. interconnections changeable from non-conductive to conductive changeable by the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/128—Molten metals, e.g. casting thereof, or melting by heating and excluding molten solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/173—Adding connections between adjacent pads or conductors, e.g. for modifying or repairing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49163—Manufacturing circuit on or in base with sintering of base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE19863638799 1985-11-14 1986-11-13 Verfahren zum elektrischen miteinanderverbinden von leitern auf einem substrat sowie dafuer geeignetes substrat Granted DE3638799A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/799,926 US4681778A (en) 1985-11-14 1985-11-14 Method and apparatus for making electrical connections utilizing a dielectric-like metal film

Publications (2)

Publication Number Publication Date
DE3638799A1 DE3638799A1 (de) 1987-05-21
DE3638799C2 true DE3638799C2 (OSRAM) 1989-10-26

Family

ID=25177102

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863638799 Granted DE3638799A1 (de) 1985-11-14 1986-11-13 Verfahren zum elektrischen miteinanderverbinden von leitern auf einem substrat sowie dafuer geeignetes substrat

Country Status (3)

Country Link
US (1) US4681778A (OSRAM)
JP (1) JPS62120049A (OSRAM)
DE (1) DE3638799A1 (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4847138A (en) * 1987-10-07 1989-07-11 Corning Glass Works Thermal writing on glass and glass-ceramic substrates
US4931323A (en) * 1987-12-10 1990-06-05 Texas Instruments Incorporated Thick film copper conductor patterning by laser
US4980225A (en) * 1988-07-12 1990-12-25 Sayles & Scheel Enterprises, Incorporated Conductive composition and method of use
US5122440A (en) * 1988-09-06 1992-06-16 Chien Chung Ping Ultraviolet curing of photosensitive polyimides
US5124238A (en) * 1988-09-06 1992-06-23 The Boeing Company Fabrication of microelectronics using photosensitive polyimides
US4931353A (en) * 1989-03-01 1990-06-05 The Boeing Company Structure and method for selectively producing a conductive region on a substrate
US4974048A (en) * 1989-03-10 1990-11-27 The Boeing Company Integrated circuit having reroutable conductive paths
FR2651083B1 (fr) * 1989-08-18 1995-12-29 Commissariat Energie Atomique Element de connexion ou deconnexion electrique, circuit integre comprenant de tels elements et procede de connexion ou de deconnexion correspondant
TW278229B (en) * 1994-12-29 1996-06-11 Siemens Ag Fuse structure for an integrated circuit device and method for manufacturing a fuse structure
US5793095A (en) * 1996-08-21 1998-08-11 Vlsi Technology, Inc. Custom laser conductor linkage for integrated circuits
JP2005129851A (ja) * 2003-10-27 2005-05-19 Disco Abrasive Syst Ltd レーザ光線を利用した加工方法
US8227278B2 (en) * 2008-09-05 2012-07-24 Semiconductor Energy Laboratory Co., Ltd. Methods for manufacturing thin film transistor and display device
US9133545B2 (en) * 2013-10-23 2015-09-15 Corning Incorporated Glass-ceramics substrates for graphene growth

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3801366A (en) * 1971-02-16 1974-04-02 J Lemelson Method of making an electrical circuit
GB1574699A (en) * 1975-10-10 1980-09-10 Luc Technologies Ltd Conductive connections
US4159414A (en) * 1978-04-25 1979-06-26 Massachusetts Institute Of Technology Method for forming electrically conductive paths
JPS5856355A (ja) * 1981-09-30 1983-04-04 Hitachi Ltd 半導体集積回路装置
JPS58115692A (ja) * 1981-12-28 1983-07-09 Fujitsu Ltd プログラマブル・リードオンリメモリのヒューズ切断方法
US4486464A (en) * 1982-09-27 1984-12-04 Sperry Corporation Method of making planarizing non-conductive layers employing conductive metals

Also Published As

Publication number Publication date
US4681778A (en) 1987-07-21
DE3638799A1 (de) 1987-05-21
JPS62120049A (ja) 1987-06-01

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee