DE2440080A1 - Verfahren zur aetzung von halbleiteraktivteilen und vorrichtung zur ausfuehrung des verfahrens - Google Patents

Verfahren zur aetzung von halbleiteraktivteilen und vorrichtung zur ausfuehrung des verfahrens

Info

Publication number
DE2440080A1
DE2440080A1 DE2440080A DE2440080A DE2440080A1 DE 2440080 A1 DE2440080 A1 DE 2440080A1 DE 2440080 A DE2440080 A DE 2440080A DE 2440080 A DE2440080 A DE 2440080A DE 2440080 A1 DE2440080 A1 DE 2440080A1
Authority
DE
Germany
Prior art keywords
template
spacers
pressure
etching
active parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE2440080A
Other languages
German (de)
English (en)
Inventor
Tibor Pakoczy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BBC BROWN BOVERI and CIE
BBC Brown Boveri AG Switzerland
Original Assignee
BBC BROWN BOVERI and CIE
BBC Brown Boveri AG Switzerland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BBC BROWN BOVERI and CIE, BBC Brown Boveri AG Switzerland filed Critical BBC BROWN BOVERI and CIE
Publication of DE2440080A1 publication Critical patent/DE2440080A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/10—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
    • H10P72/12—Vertical boat type carrier whereby the substrates are horizontally supported, e.g. comprising rod-shaped elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/10—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof using carriers specially adapted therefor, e.g. front opening unified pods [FOUP]
    • H10P72/12—Vertical boat type carrier whereby the substrates are horizontally supported, e.g. comprising rod-shaped elements
    • H10P72/123—Vertical boat type carrier whereby the substrates are horizontally supported, e.g. comprising rod-shaped elements characterised by a material, a roughness, a coating or the like

Landscapes

  • Weting (AREA)
  • Detergent Compositions (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
DE2440080A 1974-07-02 1974-08-21 Verfahren zur aetzung von halbleiteraktivteilen und vorrichtung zur ausfuehrung des verfahrens Withdrawn DE2440080A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH903374A CH573663A5 (enExample) 1974-07-02 1974-07-02

Publications (1)

Publication Number Publication Date
DE2440080A1 true DE2440080A1 (de) 1976-01-22

Family

ID=4347579

Family Applications (2)

Application Number Title Priority Date Filing Date
DE2440080A Withdrawn DE2440080A1 (de) 1974-07-02 1974-08-21 Verfahren zur aetzung von halbleiteraktivteilen und vorrichtung zur ausfuehrung des verfahrens
DE19747428330U Expired DE7428330U (de) 1974-07-02 1974-08-21 Vorrichtung zur aetzung von halbleiteraktivteilen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE19747428330U Expired DE7428330U (de) 1974-07-02 1974-08-21 Vorrichtung zur aetzung von halbleiteraktivteilen

Country Status (2)

Country Link
CH (1) CH573663A5 (enExample)
DE (2) DE2440080A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2589886A1 (fr) * 1985-09-26 1987-05-15 Nat Semiconductor Corp Systeme pour la galvanoplastie de dispositifs semi-conducteurs moules
WO2024235541A1 (de) * 2023-05-16 2024-11-21 Singulus Technologies Ag Carrier für die kantenpassivierung

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3743044A1 (de) * 1987-12-18 1989-06-29 Semikron Elektronik Gmbh Verfahren zum herstellen von halbleiterbauelementen

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2589886A1 (fr) * 1985-09-26 1987-05-15 Nat Semiconductor Corp Systeme pour la galvanoplastie de dispositifs semi-conducteurs moules
WO2024235541A1 (de) * 2023-05-16 2024-11-21 Singulus Technologies Ag Carrier für die kantenpassivierung

Also Published As

Publication number Publication date
DE7428330U (de) 1976-05-06
CH573663A5 (enExample) 1976-03-15

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Legal Events

Date Code Title Description
OF Willingness to grant licences before publication of examined application
8141 Disposal/no request for examination