DE2360903A1 - Umformer fuer logische spannungsniveaus - Google Patents
Umformer fuer logische spannungsniveausInfo
- Publication number
- DE2360903A1 DE2360903A1 DE2360903A DE2360903A DE2360903A1 DE 2360903 A1 DE2360903 A1 DE 2360903A1 DE 2360903 A DE2360903 A DE 2360903A DE 2360903 A DE2360903 A DE 2360903A DE 2360903 A1 DE2360903 A1 DE 2360903A1
- Authority
- DE
- Germany
- Prior art keywords
- field effect
- effect transistor
- connection point
- voltage
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims description 41
- 239000003990 capacitor Substances 0.000 claims description 17
- 230000005540 biological transmission Effects 0.000 claims description 13
- 230000000295 complement effect Effects 0.000 claims description 13
- 230000000694 effects Effects 0.000 claims description 7
- 208000037516 chromosome inversion disease Diseases 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000008859 change Effects 0.000 description 9
- 239000000872 buffer Substances 0.000 description 8
- 230000015654 memory Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 101000738757 Homo sapiens Phosphatidylglycerophosphatase and protein-tyrosine phosphatase 1 Proteins 0.000 description 1
- 102100037408 Phosphatidylglycerophosphatase and protein-tyrosine phosphatase 1 Human genes 0.000 description 1
- 206010065954 Stubbornness Diseases 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/01855—Interface arrangements synchronous, i.e. using clock signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K6/00—Manipulating pulses having a finite slope and not covered by one of the other main groups of this subclass
- H03K6/02—Amplifying pulses
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US00312999A US3835457A (en) | 1972-12-07 | 1972-12-07 | Dynamic mos ttl compatible |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2360903A1 true DE2360903A1 (de) | 1974-07-04 |
Family
ID=23213931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE2360903A Pending DE2360903A1 (de) | 1972-12-07 | 1973-12-06 | Umformer fuer logische spannungsniveaus |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US3835457A (enExample) |
| JP (1) | JPS4990060A (enExample) |
| DE (1) | DE2360903A1 (enExample) |
| FR (1) | FR2210052B1 (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2606932C2 (de) * | 1976-02-20 | 1983-11-10 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordnung zum Umsetzen der Pegel digitaler Signale |
| EP0397241A1 (en) * | 1989-05-09 | 1990-11-14 | Koninklijke Philips Electronics N.V. | Driver for high voltage half-bridge circuits |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2346966B2 (de) * | 1973-09-18 | 1976-07-29 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur uebertragung von signalen zwischen zwei chips mit schnellen komplementaer-mos-schaltungen |
| JPS51139223A (en) * | 1975-05-28 | 1976-12-01 | Hitachi Ltd | Mis level converter circuit |
| DE2639555C2 (de) * | 1975-09-04 | 1985-07-04 | Plessey Overseas Ltd., Ilford, Essex | Elektrische integrierte Schaltung |
| US4038567A (en) * | 1976-03-22 | 1977-07-26 | International Business Machines Corporation | Memory input signal buffer circuit |
| US4081699A (en) * | 1976-09-14 | 1978-03-28 | Mos Technology, Inc. | Depletion mode coupling device for a memory line driving circuit |
| FR2405513A1 (fr) * | 1977-10-07 | 1979-05-04 | Cii Honeywell Bull | Circuit generateur de phase de commande d'execution d'operations dans un systeme informatique |
| US4256976A (en) * | 1978-12-07 | 1981-03-17 | Texas Instruments Incorporated | Four clock phase N-channel MOS gate |
| US4291242A (en) * | 1979-05-21 | 1981-09-22 | Motorola, Inc. | Driver circuit for use in an output buffer |
| US4352996A (en) * | 1980-03-21 | 1982-10-05 | Texas Instruments Incorporated | IGFET Clock generator circuit employing MOS boatstrap capacitive drive |
| JPS5713819A (en) * | 1980-06-27 | 1982-01-23 | Oki Electric Ind Co Ltd | Output interface circuit |
| JPS5769335U (enExample) * | 1980-10-14 | 1982-04-26 | ||
| JPS57134962A (en) * | 1981-02-13 | 1982-08-20 | Toshiba Corp | Semiconductor memory and manufacture of the same |
| US4437024A (en) | 1981-10-22 | 1984-03-13 | Rca Corporation | Actively controlled input buffer |
| US4406957A (en) * | 1981-10-22 | 1983-09-27 | Rca Corporation | Input buffer circuit |
| JP2982196B2 (ja) * | 1990-02-06 | 1999-11-22 | 日本電気株式会社 | 異電源インターフェース回路 |
| JPH088709A (ja) * | 1994-06-17 | 1996-01-12 | Harris Corp | ブリッジ制御回路 |
| US5812103A (en) * | 1995-12-11 | 1998-09-22 | Supertex, Inc. | High voltage output circuit for driving gray scale flat panel displays and method therefor |
| GB9805882D0 (en) | 1998-03-20 | 1998-05-13 | Sharp Kk | Voltage level converters |
| US6917221B2 (en) * | 2003-04-28 | 2005-07-12 | International Business Machines Corporation | Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits |
| JP4617840B2 (ja) * | 2004-11-17 | 2011-01-26 | 日本電気株式会社 | ブートストラップ回路及びその駆動方法並びにシフトレジスタ回路、論理演算回路、半導体装置 |
| CN101957733B (zh) * | 2009-07-16 | 2015-02-25 | 赛恩倍吉科技顾问（深圳）有限公司 | 电脑系统 |
| US8154322B2 (en) * | 2009-12-21 | 2012-04-10 | Analog Devices, Inc. | Apparatus and method for HDMI transmission |
| US10923473B2 (en) * | 2016-02-18 | 2021-02-16 | Massachusetts Institute Of Technology | High voltage logic circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3506851A (en) * | 1966-12-14 | 1970-04-14 | North American Rockwell | Field effect transistor driver using capacitor feedback |
| US3757310A (en) * | 1972-01-03 | 1973-09-04 | Honeywell Inf Systems | Memory address selction apparatus including isolation circuits |
-
1972
- 1972-12-07 US US00312999A patent/US3835457A/en not_active Expired - Lifetime
-
1973
- 1973-12-04 JP JP48134967A patent/JPS4990060A/ja active Pending
- 1973-12-06 DE DE2360903A patent/DE2360903A1/de active Pending
- 1973-12-06 FR FR7343624A patent/FR2210052B1/fr not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2606932C2 (de) * | 1976-02-20 | 1983-11-10 | Siemens AG, 1000 Berlin und 8000 München | Schaltungsanordnung zum Umsetzen der Pegel digitaler Signale |
| EP0397241A1 (en) * | 1989-05-09 | 1990-11-14 | Koninklijke Philips Electronics N.V. | Driver for high voltage half-bridge circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2210052B1 (enExample) | 1977-06-10 |
| FR2210052A1 (enExample) | 1974-07-05 |
| JPS4990060A (enExample) | 1974-08-28 |
| US3835457A (en) | 1974-09-10 |
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