DE2340142C3 - Verfahren zur Massenproduktion von Halbleiteranordnungen mit hoher Durchbruchspannung - Google Patents

Verfahren zur Massenproduktion von Halbleiteranordnungen mit hoher Durchbruchspannung

Info

Publication number
DE2340142C3
DE2340142C3 DE2340142A DE2340142A DE2340142C3 DE 2340142 C3 DE2340142 C3 DE 2340142C3 DE 2340142 A DE2340142 A DE 2340142A DE 2340142 A DE2340142 A DE 2340142A DE 2340142 C3 DE2340142 C3 DE 2340142C3
Authority
DE
Germany
Prior art keywords
semiconductor
plate
film
base
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2340142A
Other languages
German (de)
English (en)
Other versions
DE2340142A1 (de
DE2340142B2 (de
Inventor
Yutaka Misawa
Hideyuki Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2340142A1 publication Critical patent/DE2340142A1/de
Publication of DE2340142B2 publication Critical patent/DE2340142B2/de
Application granted granted Critical
Publication of DE2340142C3 publication Critical patent/DE2340142C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7402—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10S156/918—Delaminating processes adapted for specified product, e.g. delaminating medical specimen slide
    • Y10S156/93—Semiconductive product delaminating, e.g. delaminating emiconductive wafer from underlayer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face

Landscapes

  • Thyristors (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Weting (AREA)
  • Die Bonding (AREA)
DE2340142A 1972-08-09 1973-08-08 Verfahren zur Massenproduktion von Halbleiteranordnungen mit hoher Durchbruchspannung Expired DE2340142C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7911772A JPS5218069B2 (https=) 1972-08-09 1972-08-09

Publications (3)

Publication Number Publication Date
DE2340142A1 DE2340142A1 (de) 1974-03-07
DE2340142B2 DE2340142B2 (de) 1977-07-28
DE2340142C3 true DE2340142C3 (de) 1978-03-16

Family

ID=13680958

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2340142A Expired DE2340142C3 (de) 1972-08-09 1973-08-08 Verfahren zur Massenproduktion von Halbleiteranordnungen mit hoher Durchbruchspannung

Country Status (5)

Country Link
US (1) US3913217A (https=)
JP (1) JPS5218069B2 (https=)
DE (1) DE2340142C3 (https=)
GB (1) GB1400313A (https=)
NL (1) NL161619C (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969813A (en) * 1975-08-15 1976-07-20 Bell Telephone Laboratories, Incorporated Method and apparatus for removal of semiconductor chips from hybrid circuits
FR2469000A1 (fr) * 1979-10-30 1981-05-08 Silicium Semiconducteur Ssc Structure de thyristor tres haute tension glassive et son procede de fabrication
US4571093A (en) * 1983-11-04 1986-02-18 Burroughs Corporation Method of testing plastic-packaged semiconductor devices
GB2174539B (en) * 1985-04-30 1988-12-29 Marconi Electronic Devices Semiconductor devices
DE3524301A1 (de) * 1985-07-06 1987-01-15 Semikron Gleichrichterbau Verfahren zum herstellen von halbleiterelementen
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
US5000811A (en) * 1989-11-22 1991-03-19 Xerox Corporation Precision buttable subunits via dicing
US5213590A (en) * 1989-12-20 1993-05-25 Neff Charles E Article and a method for producing an article having a high friction surface
US5236871A (en) * 1992-04-29 1993-08-17 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method for producing a hybridization of detector array and integrated circuit for readout
US6465743B1 (en) * 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
US5776798A (en) * 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
US20050155698A1 (en) * 2002-02-13 2005-07-21 Koninklijke Philips Electronis N.V. Method of manufacturing a polymeric foil
US8092734B2 (en) * 2004-05-13 2012-01-10 Aptina Imaging Corporation Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers
US7452739B2 (en) * 2006-03-09 2008-11-18 Semi-Photonics Co., Ltd. Method of separating semiconductor dies
US7968379B2 (en) * 2006-03-09 2011-06-28 SemiLEDs Optoelectronics Co., Ltd. Method of separating semiconductor dies
CN111999632B (zh) * 2019-05-27 2023-02-03 合肥晶合集成电路股份有限公司 Pn结样品的获取方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3416224A (en) * 1966-03-08 1968-12-17 Ibm Integrated semiconductor devices and fabrication methods therefor
US3432919A (en) * 1966-10-31 1969-03-18 Raytheon Co Method of making semiconductor diodes
US3508980A (en) * 1967-07-26 1970-04-28 Motorola Inc Method of fabricating an integrated circuit structure with dielectric isolation
US3681139A (en) * 1969-10-16 1972-08-01 Western Electric Co Method for handling and maintaining the orientation of a matrix of miniature electrical devices
US3608186A (en) * 1969-10-30 1971-09-28 Jearld L Hutson Semiconductor device manufacture with junction passivation
US3771219A (en) * 1970-02-05 1973-11-13 Sharp Kk Method for manufacturing semiconductor device
US3768150A (en) * 1970-02-13 1973-10-30 B Sloan Integrated circuit process utilizing orientation dependent silicon etch
US3720997A (en) * 1971-01-11 1973-03-20 Motorola Inc Eutectic plating and breaking silicon wafers

Also Published As

Publication number Publication date
NL7310947A (https=) 1974-02-12
JPS5218069B2 (https=) 1977-05-19
NL161619B (nl) 1979-09-17
DE2340142A1 (de) 1974-03-07
US3913217A (en) 1975-10-21
NL161619C (nl) 1980-02-15
GB1400313A (en) 1975-07-16
JPS4937577A (https=) 1974-04-08
DE2340142B2 (de) 1977-07-28

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee