DE2325152A1 - Verfahren zum herstellen von halbleiterstrukturen mittels der planartechnik - Google Patents

Verfahren zum herstellen von halbleiterstrukturen mittels der planartechnik

Info

Publication number
DE2325152A1
DE2325152A1 DE2325152A DE2325152A DE2325152A1 DE 2325152 A1 DE2325152 A1 DE 2325152A1 DE 2325152 A DE2325152 A DE 2325152A DE 2325152 A DE2325152 A DE 2325152A DE 2325152 A1 DE2325152 A1 DE 2325152A1
Authority
DE
Germany
Prior art keywords
semiconductor
oxidized
silicon
dopant
arsenic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE2325152A
Other languages
German (de)
English (en)
Inventor
Guenter Helmut Schwuttke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2325152A1 publication Critical patent/DE2325152A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
    • H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/06—Gettering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/155—Solid solubility

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Bipolar Transistors (AREA)
  • Led Devices (AREA)
DE2325152A 1972-05-22 1973-05-18 Verfahren zum herstellen von halbleiterstrukturen mittels der planartechnik Withdrawn DE2325152A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00255468A US3821038A (en) 1972-05-22 1972-05-22 Method for fabricating semiconductor structures with minimum crystallographic defects

Publications (1)

Publication Number Publication Date
DE2325152A1 true DE2325152A1 (de) 1973-12-06

Family

ID=22968459

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2325152A Withdrawn DE2325152A1 (de) 1972-05-22 1973-05-18 Verfahren zum herstellen von halbleiterstrukturen mittels der planartechnik

Country Status (7)

Country Link
US (1) US3821038A (https=)
JP (1) JPS5516373B2 (https=)
CA (1) CA994653A (https=)
DE (1) DE2325152A1 (https=)
FR (1) FR2185858B1 (https=)
GB (1) GB1421444A (https=)
IT (1) IT981609B (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970431A (en) * 1974-01-23 1976-07-20 Stanford Research Institute Carbon monoxide gas detector
US4009058A (en) * 1975-06-16 1977-02-22 Rca Corporation Method of fabricating large area, high voltage PIN photodiode devices
JPS60117665A (ja) * 1983-11-30 1985-06-25 Toshiba Corp サイリスタの製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2055162A1 (de) * 1969-11-10 1971-05-19 Ibm Verfahren zur Isolationsbereichbil dung im Halbleitersubstrat einer monohthi sehen Halbleitervorrichtung

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1288029A (https=) * 1970-02-07 1972-09-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2055162A1 (de) * 1969-11-10 1971-05-19 Ibm Verfahren zur Isolationsbereichbil dung im Halbleitersubstrat einer monohthi sehen Halbleitervorrichtung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Bell System Technical Journal, Bd. 39, 1960, S. 205-233 *

Also Published As

Publication number Publication date
GB1421444A (en) 1976-01-21
IT981609B (it) 1974-10-10
FR2185858A1 (https=) 1974-01-04
JPS5516373B2 (https=) 1980-05-01
CA994653A (en) 1976-08-10
US3821038A (en) 1974-06-28
JPS4929064A (https=) 1974-03-15
FR2185858B1 (https=) 1977-08-19

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