DE2324769A1 - Speicherschaltung - Google Patents
SpeicherschaltungInfo
- Publication number
- DE2324769A1 DE2324769A1 DE19732324769 DE2324769A DE2324769A1 DE 2324769 A1 DE2324769 A1 DE 2324769A1 DE 19732324769 DE19732324769 DE 19732324769 DE 2324769 A DE2324769 A DE 2324769A DE 2324769 A1 DE2324769 A1 DE 2324769A1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- signal
- memory
- address
- digit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
- G11C11/4023—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh using field effect transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Description
Fig. 2 die Wellenformen der Taktsignale, die zum Betrieb
Adressenpuffer 1-1 bis 1-9,/für den Betrieb des Adressenpuffers,
ein System, des/Prinzip in S1Ig. 3 gezeigt ist. Gemäß 3?ig. 3
das Ende der Datenübertragung anzeigenden Signales R4 wird der Taktimpuls 04 in einer Schaltung 74 und der Taktimpuls fo in einer Schaltung 75 erzeugt.
Claims (3)
- - 26 Patentansprücheη J Speicherschaltung mit Feldeffekttransistören mit isoliertem Gatter (IGS1ET), gekennzeichnet durch eine erste Schaltung, die ein erstes Signal in Abhängigkeit von dem Ende der Durchführung von einer der Schaltungsfunktionen, die in der Speicherschaltung durchführbar sind, und durch eine zweite Schaltung, die das erste Signal empfängt und ein Taktsignal erzeugt, um den Beginn der Durchführung der nachfolgenden Funktion der Schaltungsfunktionen zu steuern.
- 2. Speicherschaltung nach Anspruch 1, dadurch gekennzeichnet, daß die Speicherschaltung eine Vielzahl von Dekoderschaltungen (3,3') zum Dekodieren von Eingangsadressensignalen aufweist, wobei jede Dekoderschaltung (3»3') aus einer ODER-Schaltung oder einer NOE-Schaltung besteht, und daß die erste Schaltung das erste Signal in Abhängigkeit von dem Ende der von den Dekoderschaltungen (3»3f) durchgeführten Dekodierung erzeugt, wobei die erste Schaltung aus einer ODER-'--.. tSchaltung oder einer NOR-Schaltung gebildet ist, die als Eingangssignale sowohl die wahren als auch die komplementären Signale von einem der Eingangsadressensignale empfängt.
- 3.Speicherschaltung nach Anspruch 1, dadurch gekennzeichnet, daß die erste Schaltung das erste Signal in Abhängigkeit von dem Ende des Auslesens gespeicherter Information aus den Speicherzellen der ausgewählten Adressenleitung, auf die309849/0895Ziffernleitungen erzeugt, und daß die erste Schaltung wei- I tere Speicherzellen aufweist, die jeweils mit jeder Adressenleitung und einer anderen Ziffernleitung verbunden sind, die mit allen anderen Speicherzellen verbunden ist, wobei die weitere Speicherzelle bei Verbindung mit einer ausgewählten Adressenleitung das Niveau der anderen Ziffernleitung ändert.Speicherschaltung nach Anspruch 1, dadurch gekennzeichnet, daß die Speicherschaltung ein Paar von Ziffernleitungen pro Speicherzelle aufweist, daß eine Information, die aus einer Speicherzelle auf eine der paarweise vorgesehenen Ziffernleitungen ausgelesen ist, an die andere der paarweise vorgesehene Ziffernleitungen übertragen wird, daß die erste Schaltung das erste Signal in Abhängigkeit von dem Ende der Übertragung der Information erzeugt und einen Eingangsanschluß aufweist, der zur Aufnahme eines zweiten Taktsignales geeignet ist, das die Übertragung der Information steuert, und daß schliesslich eine Ziffernleitung und eine Einrichtung vorgesehen ist, um das Niveau der zuletzt er-merwähnten Ziffernleitung im/dann zu ändern, wenn das zweite Taktsignal an den Eingangsanschluß angelegt wird.309849/0895Leerseite
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4887672A JPS5240937B2 (de) | 1972-05-16 | 1972-05-16 |
Publications (3)
Publication Number | Publication Date |
---|---|
DE2324769A1 true DE2324769A1 (de) | 1973-12-06 |
DE2324769B2 DE2324769B2 (de) | 1978-12-21 |
DE2324769C3 DE2324769C3 (de) | 1987-07-09 |
Family
ID=12815473
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19732324769 Expired DE2324769C3 (de) | 1972-05-16 | 1973-05-16 | Steuerschaltung für einen Datenspeicher mit IG-FET's |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS5240937B2 (de) |
DE (1) | DE2324769C3 (de) |
FR (1) | FR2184865B1 (de) |
GB (1) | GB1438861A (de) |
IT (1) | IT987474B (de) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2545313A1 (de) | 1974-10-08 | 1976-04-29 | Mostek Corp | Dynamischer misfet randomspeicher in integrierter schaltung |
US3964030A (en) * | 1973-12-10 | 1976-06-15 | Bell Telephone Laboratories, Incorporated | Semiconductor memory array |
DE2625007A1 (de) | 1975-06-04 | 1977-02-10 | Hitachi Ltd | Adressenpufferschaltung in einem halbleiterspeicher |
DE2724646A1 (de) | 1976-06-01 | 1977-12-15 | Texas Instruments Inc | Halbleiterspeicheranordnung |
DE2716459A1 (de) * | 1976-04-15 | 1978-01-19 | Nat Semiconductor Corp | Dynamische mos-speicheranordnung fuer direktzugriff |
DE2760462C2 (de) * | 1976-06-01 | 1994-06-30 | Texas Instruments Inc | Halbleiterspeicheranordnung |
DE10031433B4 (de) * | 1999-06-28 | 2012-05-16 | Hyundai Electronics Industries Co., Ltd. | Speichervorrichtung mit Paketbefehl |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5011632A (de) * | 1973-06-01 | 1975-02-06 | ||
JPS51163830U (de) * | 1975-06-20 | 1976-12-27 | ||
JPS5284929A (en) * | 1976-01-07 | 1977-07-14 | Hitachi Ltd | Memory system |
JPS52106640A (en) * | 1976-03-05 | 1977-09-07 | Hitachi Ltd | Memory peripheral circuit |
JPS5325323A (en) * | 1976-08-23 | 1978-03-09 | Hitachi Ltd | Pre-sense amplifier |
JPS5360125A (en) * | 1976-11-11 | 1978-05-30 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory unit |
JPS5453652A (en) * | 1977-10-07 | 1979-04-27 | Denyo Co Ltd | Battery welder |
JPH0124644Y2 (de) * | 1979-08-28 | 1989-07-26 | ||
US4539661A (en) * | 1982-06-30 | 1985-09-03 | Fujitsu Limited | Static-type semiconductor memory device |
JPS5956292A (ja) * | 1982-09-24 | 1984-03-31 | Hitachi Ltd | 半導体記憶装置 |
JPS6075510A (ja) * | 1983-09-30 | 1985-04-27 | Mitsubishi Heavy Ind Ltd | 連続製鋼炉における冷材スクラツプの供給方法 |
JPS60242593A (ja) * | 1984-05-16 | 1985-12-02 | Hitachi Micro Comput Eng Ltd | 半導体記憶装置 |
JPH0736273B2 (ja) * | 1984-11-26 | 1995-04-19 | 株式会社日立製作所 | 半導体集積回路 |
DE3745016C2 (de) * | 1986-11-11 | 1996-01-18 | Mitsubishi Electric Corp | Halbleiterspeichereinrichtung |
JP2511910B2 (ja) * | 1986-11-11 | 1996-07-03 | 三菱電機株式会社 | 半導体記憶装置 |
JPS63275093A (ja) * | 1987-05-06 | 1988-11-11 | Nec Corp | 半導体記憶装置 |
US4926387A (en) * | 1988-12-27 | 1990-05-15 | Intel Corporation | Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells |
GB2360113B (en) * | 2000-03-08 | 2004-11-10 | Seiko Epson Corp | Dynamic random access memory |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1449713A1 (de) * | 1963-10-02 | 1969-03-13 | Automatic Telephone & Elect | Magnetkernmatrizen-Datenspeichervorrichtung |
-
1972
- 1972-05-16 JP JP4887672A patent/JPS5240937B2/ja not_active Expired
-
1973
- 1973-05-15 IT IT2413773A patent/IT987474B/it active
- 1973-05-15 FR FR7317551A patent/FR2184865B1/fr not_active Expired
- 1973-05-16 DE DE19732324769 patent/DE2324769C3/de not_active Expired
- 1973-05-16 GB GB2336073A patent/GB1438861A/en not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1449713A1 (de) * | 1963-10-02 | 1969-03-13 | Automatic Telephone & Elect | Magnetkernmatrizen-Datenspeichervorrichtung |
Non-Patent Citations (9)
Title |
---|
B.G. Watkins: A Low-Power Multiphase Circuit Technique. In: IEEE Journal of Solid-State Circuits, Vol. SC-2, No.4, Dezember 1967, S. 213-220 * |
Burton R. Tunzi: MOS random-access. array. In: Electronics, 20.01.1969, S. 102-105 * |
Circuits, Vol. SC-5, Nr. 5, Okt. 1970, S. 181-186 |
Electronics, 16.02.70, S. 109-115 IEEE Journal of Solid-State |
In Betracht gezogene ältere Anmeldung: DE-OS 23 24 769 |
J.Karp: Use four phase MOS IC logic. In: Electronic Design 7, 1. April 1967, S. 62-66 * |
L.M.Terman: MOSFET Memory Circuits. In: Proceedings of the IEEE, Vol. 59, No. 7, Juli 1971, S. 1044-1058 * |
Tietze, Schenk: Halbleiter-Schaltungstechnik, Springer-Verlag, 1971, S. 479-483 * |
Vadasz, Chua, Grove: Semiconductor random-access memories. In: IEEE Spectrum, Mai 1971, S. 40-48 * |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3964030A (en) * | 1973-12-10 | 1976-06-15 | Bell Telephone Laboratories, Incorporated | Semiconductor memory array |
DE2545313A1 (de) | 1974-10-08 | 1976-04-29 | Mostek Corp | Dynamischer misfet randomspeicher in integrierter schaltung |
DE2559801C2 (de) * | 1974-10-08 | 1987-02-26 | Mostek Corp. (n.d.Ges.d.Staates Delaware), Carrollton, Tex. | Verfahren zum sequentiellen Steuern der Funktionseinheiten eines dynamischen Randomspeichers |
DE2625007A1 (de) | 1975-06-04 | 1977-02-10 | Hitachi Ltd | Adressenpufferschaltung in einem halbleiterspeicher |
DE2716459A1 (de) * | 1976-04-15 | 1978-01-19 | Nat Semiconductor Corp | Dynamische mos-speicheranordnung fuer direktzugriff |
DE2724646A1 (de) | 1976-06-01 | 1977-12-15 | Texas Instruments Inc | Halbleiterspeicheranordnung |
DE2760462C2 (de) * | 1976-06-01 | 1994-06-30 | Texas Instruments Inc | Halbleiterspeicheranordnung |
DE10031433B4 (de) * | 1999-06-28 | 2012-05-16 | Hyundai Electronics Industries Co., Ltd. | Speichervorrichtung mit Paketbefehl |
Also Published As
Publication number | Publication date |
---|---|
JPS5240937B2 (de) | 1977-10-15 |
IT987474B (it) | 1975-02-20 |
FR2184865B1 (de) | 1980-03-07 |
DE2324769C3 (de) | 1987-07-09 |
FR2184865A1 (de) | 1973-12-28 |
JPS4914052A (de) | 1974-02-07 |
DE2324769B2 (de) | 1978-12-21 |
GB1438861A (en) | 1976-06-09 |
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Legal Events
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BHJ | Nonpayment of the annual fee | ||
OI | Miscellaneous see part 1 | ||
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