DE2318550C3 - Speicheranordnung - Google Patents

Speicheranordnung

Info

Publication number
DE2318550C3
DE2318550C3 DE2318550A DE2318550A DE2318550C3 DE 2318550 C3 DE2318550 C3 DE 2318550C3 DE 2318550 A DE2318550 A DE 2318550A DE 2318550 A DE2318550 A DE 2318550A DE 2318550 C3 DE2318550 C3 DE 2318550C3
Authority
DE
Germany
Prior art keywords
transistors
memory cells
read
resistance
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2318550A
Other languages
German (de)
English (en)
Other versions
DE2318550B2 (enExample
DE2318550A1 (de
Inventor
Jonothan Whipple Saunderstown R.I. Rose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2318550A1 publication Critical patent/DE2318550A1/de
Publication of DE2318550B2 publication Critical patent/DE2318550B2/de
Application granted granted Critical
Publication of DE2318550C3 publication Critical patent/DE2318550C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8311—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE2318550A 1972-06-28 1973-04-12 Speicheranordnung Expired DE2318550C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26686072A 1972-06-28 1972-06-28

Publications (3)

Publication Number Publication Date
DE2318550A1 DE2318550A1 (de) 1974-01-31
DE2318550B2 DE2318550B2 (enExample) 1980-07-31
DE2318550C3 true DE2318550C3 (de) 1981-04-02

Family

ID=23016280

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2318550A Expired DE2318550C3 (de) 1972-06-28 1973-04-12 Speicheranordnung

Country Status (7)

Country Link
US (1) US3747078A (enExample)
JP (1) JPS5330465B2 (enExample)
CA (1) CA992204A (enExample)
DE (1) DE2318550C3 (enExample)
FR (1) FR2191201B1 (enExample)
GB (1) GB1363049A (enExample)
IT (1) IT983949B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5059198A (enExample) * 1973-09-28 1975-05-22
DE2460150C2 (de) * 1974-12-19 1984-07-12 Ibm Deutschland Gmbh, 7000 Stuttgart Monolitisch integrierbare Speicheranordnung
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置
US4208730A (en) * 1978-08-07 1980-06-17 Rca Corporation Precharge circuit for memory array
JPS5562586A (en) * 1978-10-30 1980-05-12 Fujitsu Ltd Semiconductor memory device
US4498122A (en) * 1982-12-29 1985-02-05 At&T Bell Laboratories High-speed, high pin-out LSI chip package
DE3313441A1 (de) * 1983-04-13 1984-10-18 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher
JPS62238670A (ja) * 1986-04-09 1987-10-19 Mitsubishi Electric Corp 半導体記憶装置
CN100459304C (zh) * 2003-01-07 2009-02-04 皇家飞利浦电子股份有限公司 高电压连接器
US20080031029A1 (en) * 2006-08-05 2008-02-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memory device with split bit-line structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL284927A (enExample) * 1961-11-01
US3585399A (en) * 1968-10-28 1971-06-15 Honeywell Inc A two impedance branch termination network for interconnecting two systems for bidirectional transmission
US3588846A (en) * 1968-12-05 1971-06-28 Ibm Storage cell with variable power level
US3706078A (en) * 1970-09-11 1972-12-12 Licentia Gmbh Memory storage matrix with line input and complementary delay at output

Also Published As

Publication number Publication date
DE2318550B2 (enExample) 1980-07-31
JPS4944634A (enExample) 1974-04-26
IT983949B (it) 1974-11-11
FR2191201A1 (enExample) 1974-02-01
US3747078A (en) 1973-07-17
GB1363049A (en) 1974-08-14
JPS5330465B2 (enExample) 1978-08-26
FR2191201B1 (enExample) 1976-04-23
CA992204A (en) 1976-06-29
DE2318550A1 (de) 1974-01-31

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Legal Events

Date Code Title Description
OD Request for examination
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee