DE2251823A1 - Halbleiterelement und herstellungsverfahren - Google Patents

Halbleiterelement und herstellungsverfahren

Info

Publication number
DE2251823A1
DE2251823A1 DE2251823A DE2251823A DE2251823A1 DE 2251823 A1 DE2251823 A1 DE 2251823A1 DE 2251823 A DE2251823 A DE 2251823A DE 2251823 A DE2251823 A DE 2251823A DE 2251823 A1 DE2251823 A1 DE 2251823A1
Authority
DE
Germany
Prior art keywords
layer
mesa
semiconductor
embedding
shaped elevation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE2251823A
Other languages
German (de)
English (en)
Inventor
Fritz Guenter Dipl Phys D Adam
Albrecht Dipl Phys Dr Ing Renz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE2251823A priority Critical patent/DE2251823A1/de
Priority to US405222A priority patent/US3869786A/en
Priority to AU61364/73A priority patent/AU6136473A/en
Priority to IT30150/73A priority patent/IT995885B/it
Priority to FR7337186A priority patent/FR2204045B1/fr
Priority to JP48117735A priority patent/JPS4975077A/ja
Priority to NL7314500A priority patent/NL7314500A/xx
Publication of DE2251823A1 publication Critical patent/DE2251823A1/de
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0128—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising multiple local oxidation process steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
DE2251823A 1972-10-21 1972-10-21 Halbleiterelement und herstellungsverfahren Ceased DE2251823A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE2251823A DE2251823A1 (de) 1972-10-21 1972-10-21 Halbleiterelement und herstellungsverfahren
US405222A US3869786A (en) 1972-10-21 1973-10-10 Semiconductor component and its method of manufacturing
AU61364/73A AU6136473A (en) 1972-10-21 1973-10-15 Semiconductor component
IT30150/73A IT995885B (it) 1972-10-21 1973-10-16 Componente a semiconduttore e meto do per la fabbricazione dello stesso
FR7337186A FR2204045B1 (enExample) 1972-10-21 1973-10-18
JP48117735A JPS4975077A (enExample) 1972-10-21 1973-10-19
NL7314500A NL7314500A (enExample) 1972-10-21 1973-10-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2251823A DE2251823A1 (de) 1972-10-21 1972-10-21 Halbleiterelement und herstellungsverfahren

Publications (1)

Publication Number Publication Date
DE2251823A1 true DE2251823A1 (de) 1974-05-02

Family

ID=5859760

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2251823A Ceased DE2251823A1 (de) 1972-10-21 1972-10-21 Halbleiterelement und herstellungsverfahren

Country Status (7)

Country Link
US (1) US3869786A (enExample)
JP (1) JPS4975077A (enExample)
AU (1) AU6136473A (enExample)
DE (1) DE2251823A1 (enExample)
FR (1) FR2204045B1 (enExample)
IT (1) IT995885B (enExample)
NL (1) NL7314500A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1085486B (it) * 1977-05-30 1985-05-28 Ates Componenti Elettron Struttura a semiconduttore integrata monolitica con giunzioni planari schermate da campi elettrostatici esterni
US4219379A (en) * 1978-09-25 1980-08-26 Mostek Corporation Method for making a semiconductor device
US4268951A (en) * 1978-11-13 1981-05-26 Rockwell International Corporation Submicron semiconductor devices
DE2902665A1 (de) * 1979-01-24 1980-08-07 Siemens Ag Verfahren zum herstellen von integrierten mos-schaltungen in silizium-gate- technologie
CA1204525A (en) * 1982-11-29 1986-05-13 Tetsu Fukano Method for forming an isolation region for electrically isolating elements
JP3594779B2 (ja) 1997-06-24 2004-12-02 株式会社ルネサステクノロジ 半導体装置の製造方法
US6190952B1 (en) * 1999-03-03 2001-02-20 Advanced Micro Devices, Inc. Multiple semiconductor-on-insulator threshold voltage circuit
US6455903B1 (en) 2000-01-26 2002-09-24 Advanced Micro Devices, Inc. Dual threshold voltage MOSFET by local confinement of channel depletion layer using inert ion implantation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3534234A (en) * 1966-12-15 1970-10-13 Texas Instruments Inc Modified planar process for making semiconductor devices having ultrafine mesa type geometry
NL164424C (nl) * 1970-06-04 1980-12-15 Philips Nv Werkwijze voor het vervaardigen van een veldeffect- transistor met een geisoleerde stuurelektrode, waarbij een door een tegen oxydatie maskerende laag vrijgelaten deel van het oppervlak van een siliciumlichaam aan een oxydatiebehandeling wordt onderworpen ter verkrijging van een althans gedeeltelijk in het siliciumlichaam verzonken siliciumoxydelaag.
NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
US3815223A (en) * 1971-02-08 1974-06-11 Signetics Corp Method for making semiconductor structure with dielectric and air isolation
US3761327A (en) * 1971-03-19 1973-09-25 Itt Planar silicon gate mos process

Also Published As

Publication number Publication date
IT995885B (it) 1975-11-20
FR2204045B1 (enExample) 1977-05-27
US3869786A (en) 1975-03-11
JPS4975077A (enExample) 1974-07-19
FR2204045A1 (enExample) 1974-05-17
NL7314500A (enExample) 1974-04-23
AU6136473A (en) 1975-04-17

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Legal Events

Date Code Title Description
OD Request for examination
8131 Rejection