DE2124764C3 - Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung

Info

Publication number
DE2124764C3
DE2124764C3 DE2124764A DE2124764A DE2124764C3 DE 2124764 C3 DE2124764 C3 DE 2124764C3 DE 2124764 A DE2124764 A DE 2124764A DE 2124764 A DE2124764 A DE 2124764A DE 2124764 C3 DE2124764 C3 DE 2124764C3
Authority
DE
Germany
Prior art keywords
area
bombardment
layer
epitaxial layer
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2124764A
Other languages
German (de)
English (en)
Other versions
DE2124764A1 (de
DE2124764B2 (de
Inventor
John Martin Reigate Surrey Shannon (Grossbritannien)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2124764A1 publication Critical patent/DE2124764A1/de
Publication of DE2124764B2 publication Critical patent/DE2124764B2/de
Application granted granted Critical
Publication of DE2124764C3 publication Critical patent/DE2124764C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P34/00—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices
    • H10P34/40—Irradiation with electromagnetic or particle radiation of wafers, substrates or parts of devices with high-energy radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H10D62/138—Pedestal collectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/128—Proton bombardment of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/151—Simultaneous diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/923—Diffusion through a layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/965—Shaped junction formation

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE2124764A 1970-05-22 1971-05-19 Verfahren zur Herstellung einer Halbleiteranordnung Expired DE2124764C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2502970 1970-05-22

Publications (3)

Publication Number Publication Date
DE2124764A1 DE2124764A1 (de) 1971-12-02
DE2124764B2 DE2124764B2 (de) 1978-03-30
DE2124764C3 true DE2124764C3 (de) 1978-11-30

Family

ID=10221069

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2124764A Expired DE2124764C3 (de) 1970-05-22 1971-05-19 Verfahren zur Herstellung einer Halbleiteranordnung

Country Status (7)

Country Link
US (1) US3761319A (enExample)
JP (1) JPS505022B1 (enExample)
CH (1) CH530714A (enExample)
DE (1) DE2124764C3 (enExample)
FR (1) FR2090238B1 (enExample)
GB (1) GB1307546A (enExample)
NL (1) NL7106777A (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1420065A (en) * 1972-01-31 1976-01-07 Mullard Ltd Methods of manufacturing semiconductor bodies
SE361232B (enExample) * 1972-11-09 1973-10-22 Ericsson Telefon Ab L M
FR2257998B1 (enExample) * 1974-01-10 1976-11-26 Commissariat Energie Atomique
GB1502165A (en) * 1974-04-10 1978-02-22 Sony Corp Semiconductor devices
US3974560A (en) * 1974-05-02 1976-08-17 Rca Corporation Method of making a bipolar transistor
US3943555A (en) * 1974-05-02 1976-03-09 Rca Corporation SOS Bipolar transistor
US3982967A (en) * 1975-03-26 1976-09-28 Ibm Corporation Method of proton-enhanced diffusion for simultaneously forming integrated circuit regions of varying depths
US4157268A (en) * 1977-06-16 1979-06-05 International Business Machines Corporation Localized oxidation enhancement for an integrated injection logic circuit
US4133701A (en) * 1977-06-29 1979-01-09 General Motors Corporation Selective enhancement of phosphorus diffusion by implanting halogen ions
US4203781A (en) * 1978-12-27 1980-05-20 Bell Telephone Laboratories, Incorporated Laser deformation of semiconductor junctions
JPS57139965A (en) * 1981-02-24 1982-08-30 Toshiba Corp Manufacture of semiconductor device
US4644383A (en) * 1985-04-08 1987-02-17 Harris Corporation Subcollector for oxide and junction isolated IC's
ATE116599T1 (de) * 1989-01-13 1995-01-15 Canon Kk Aufzeichnungskopf.
US5943579A (en) * 1997-02-14 1999-08-24 Micron Technology, Inc. Method for forming a diffusion region in a semiconductor device
US6995068B1 (en) * 2000-06-09 2006-02-07 Newport Fab, Llc Double-implant high performance varactor and method for manufacturing same
DE10361134B4 (de) * 2003-12-23 2014-10-23 Infineon Technologies Ag Verfahren zur Herstellung eines p-Emitters eines IGBTs, einer Anode, einer Diode und einer Anode eines asymmetrischen Thyristors.
DE102004029945B4 (de) * 2004-06-21 2008-01-17 Infineon Technologies Ag Verfahren zur Herstellung einer oberflächennahen dotierten Zone in einem Halbleiterkörper
US20100314695A1 (en) * 2009-06-10 2010-12-16 International Rectifier Corporation Self-aligned vertical group III-V transistor and method for fabricated same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL299036A (enExample) * 1962-08-03
CH522290A (de) * 1968-12-20 1972-06-15 Siemens Ag Verfahren zur Getterung schnell diffundierender Verunreinigungen in Halbleiterkristallen

Also Published As

Publication number Publication date
NL7106777A (enExample) 1971-11-24
CH530714A (de) 1972-11-15
DE2124764A1 (de) 1971-12-02
JPS505022B1 (enExample) 1975-02-27
DE2124764B2 (de) 1978-03-30
FR2090238B1 (enExample) 1976-06-11
US3761319A (en) 1973-09-25
GB1307546A (en) 1973-02-21
FR2090238A1 (enExample) 1972-01-14

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee