DE2047612A1 - Halbleiteranordnung - Google Patents
HalbleiteranordnungInfo
- Publication number
- DE2047612A1 DE2047612A1 DE19702047612 DE2047612A DE2047612A1 DE 2047612 A1 DE2047612 A1 DE 2047612A1 DE 19702047612 DE19702047612 DE 19702047612 DE 2047612 A DE2047612 A DE 2047612A DE 2047612 A1 DE2047612 A1 DE 2047612A1
- Authority
- DE
- Germany
- Prior art keywords
- transistor
- substrate
- clock pulse
- transistors
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 44
- 239000000758 substrate Substances 0.000 claims description 31
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000013256 coordination polymer Substances 0.000 description 18
- 230000003071 parasitic effect Effects 0.000 description 15
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Shift Register Type Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Static Random-Access Memory (AREA)
- Logic Circuits (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP44077645A JPS5126772B1 (enrdf_load_stackoverflow) | 1969-09-29 | 1969-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2047612A1 true DE2047612A1 (de) | 1971-04-22 |
Family
ID=13639614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19702047612 Withdrawn DE2047612A1 (de) | 1969-09-29 | 1970-09-28 | Halbleiteranordnung |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5126772B1 (enrdf_load_stackoverflow) |
| DE (1) | DE2047612A1 (enrdf_load_stackoverflow) |
| FR (1) | FR2063062B1 (enrdf_load_stackoverflow) |
| GB (1) | GB1309139A (enrdf_load_stackoverflow) |
| NL (1) | NL166819C (enrdf_load_stackoverflow) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1459892A (fr) * | 1964-08-20 | 1966-06-17 | Texas Instruments Inc | Dispositifs semi-conducteurs |
| GB1131675A (en) * | 1966-07-11 | 1968-10-23 | Hitachi Ltd | Semiconductor device |
| GB1170705A (en) * | 1967-02-27 | 1969-11-12 | Hitachi Ltd | An Insulated Gate Type Field Effect Semiconductor Device having a Breakdown Preventing Circuit Device and a method of manufacturing the same |
-
1969
- 1969-09-29 JP JP44077645A patent/JPS5126772B1/ja active Pending
-
1970
- 1970-09-25 GB GB4582770A patent/GB1309139A/en not_active Expired
- 1970-09-28 DE DE19702047612 patent/DE2047612A1/de not_active Withdrawn
- 1970-09-29 FR FR7035188A patent/FR2063062B1/fr not_active Expired
- 1970-09-29 NL NL7014289.A patent/NL166819C/xx not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| GB1309139A (en) | 1973-03-07 |
| NL7014289A (enrdf_load_stackoverflow) | 1971-03-31 |
| JPS5126772B1 (enrdf_load_stackoverflow) | 1976-08-09 |
| FR2063062A1 (enrdf_load_stackoverflow) | 1971-07-02 |
| NL166819B (nl) | 1981-04-15 |
| NL166819C (nl) | 1981-09-15 |
| FR2063062B1 (enrdf_load_stackoverflow) | 1974-08-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8139 | Disposal/non-payment of the annual fee |