DE2047612A1 - Semiconductor device - Google Patents

Description

SONY CORPORATION (SONY KABUSHIKIKAISHA) Tokyo / Japan

Semiconductor device

The invention relates to a semiconductor arrangement, in particular a semiconductor arrangement with a memory circuit, the metal-insulated semiconductor transistors (MIS transistors) contains.

Various memory circuits with MIS or MOS transistors have already been proposed, for example in FIG the US application Ser.No. 868 8OO of 23 January 1969 in general such a memory circuit requires a clock pulse as a time base; a clock pulse feed line is provided for this purpose. These The lead is provided on an insulating layer which is located on the semiconductor substrate. It arises as a result an inverse layer on the surface of the substrate by an electric field generated by the clock signal, creating a channel arises. There is now the possibility that the clock signal lead acts as a gate electrode and thus one in the substrate unwanted, parasitic MIS transistor transistor, which is an im Memory circuit eliminates the stored signal and thus causes a wrong puncture. One can train such Avoid the inverse layer by reinforcing the insulating layer as much as possible; However, this is difficult to manufacture; the thickness of the substrate is also limited because of cracking of the insulating layer; it also increases the possibility bending of the substrate due to the difference in thermal coefficient between the insulating layer and

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the substrate. It has thus been found to be very difficult to provide a semiconductor device such as those mentioned above Does not have defects.

The invention is based on a semiconductor arrangement with a substrate of one conductivity type, one on the substrate formed insulating layer, a number of formed in the substrate, metal-insulated semiconductor transistors, each a source region and a drain region of the opposite one Conductivity type such as substrate and a gate electrode on the insulating layer, furthermore with a conductive layer provided on the insulating layer for supplying a clock pulse to the transistors.

In the case of such a semiconductor arrangement, the invention consists in "that in the substrate a diffusion region of the opposite

set conductivity type against subs the conductive layer is connected.

Set conductivity type against the substrate and formed

In the semiconductor arrangement according to the invention can therefore the insulating layer under the clock signal feed line can be made as thin as possible. This makes manufacturing easier the semiconductor device and reduces the risk of incorrect operation.

An embodiment of the invention is illustrated in the drawing. Show it

Pig.l is a circuit diagram of one consisting of MIS transistors Flip-flop circuit forming part of a memory circuit;

2 shows a number of diagrams for explanation

the operation of the circuit according to Fig.l;

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Pig.3 a schematic plan view of a usual Semiconductor device j

Fig.il a section along the line IV-IV of Fig. 3; FIG. 5 shows an equivalent circuit diagram of the arrangement according to FIG. 4;

6 shows a section corresponding to FIG. 4 through an exemplary embodiment the semiconductor device according to the invention;

7 shows a circuit diagram to explain the invention.

Fig.l shows an embodiment of the mentioned earlier already proposed circuit in its application in a flip-flop circuit, which forms part of a memory circuit.

The circuit contains MIS transistors M. to Mg, which in the illustrated embodiment are formed by enhancement-type N-channel transistors with an insulated gate. The gate of the transistor M ₁ is connected to the input terminal t * . The drain electrode is connected to the connection point X ₁ of the drain of the transistor M _? and source of transistor M, connected. The source electrode of M ^ is connected to a first clock pulse input terminal t ₁ . The gate and source of the transistor Mp are connected to the input terminal t ₁ ; the gate of the transistor M is connected to a second clock pulse input terminal tp.

A circuit, which forms a counterpart to the circuit consisting of the transistors M ₁ to M, contains the transistors Mj, to M ^. The gate of transistor Mj. is connected to the drain electrode of the transistor M_ (cf. Xp) · The drain electrode of M ^. is at the connection point X, of the drain of the transistor M- and the source of the transistor Mr

5 ο

connected. The source of transistor Mh is

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connected to the input terminal tp. The gate and source of the transistor ML are connected to the input terminal T _? tied together; the gate electrode of the transistor Mg is connected to the input terminal t * and the drain electrode of Mg is connected to an output terminal T ₂ . Transistors M. and Mg are formed on a common, grounded semiconductor substrate _<.

The input terminal t ^ is with a first clock pulse CP. (see Pig.2A), while the input _{terminal t 2 is} supplied with a second clock pulse CPp (see Pig.2B) which is offset by a predetermined phase angle _{with respect to the first clock pulse CP 1.} The selected embodiment is explained in the following with the aid of positive logic, the higher level of two values being denoted as "1" and the lower level as "O".

The input connection T ₁ is fed with an input _{pulse S 1} (see Fig. 2C) which is synchronized _{with the clock pulse CP 1.} If the input pulse S _{1 has} the value "1", the transistor M _{1 is} in the conductive state. If the input pulse S _{1 has} the value "0", the transistor M _{1 is} in the non-conductive switching state.

If the first clock pulse CP. fed to the input terminal t ₁ , it arrives at the gate of the transistor M n; the transistor M_ is consequently conductive when the clock pulse CP _{1 has} the value "1". The clock pulse CP _{1 also} reaches the source electrode of the transistor M; will the tran-

2 sistor M ₁ held in the non-conductive switching state by the input _{pulse S 1 , the potential at the connection point X 1} is raised to "1" by the clock pulse CP _1; at the same time, a capacitance between the connection point X ₁ and the semiconductor substrate is _{charged by the clock pulse CP 1 of} the value "1"; accordingly, the connection point X ₁ is held at the value "1" by the charge.

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If, on the other hand, the transistor M ₁ is brought into the conductive switching state by the input pulse S _{1 , the charge stored between the connection point X 1} and the semiconductor substrate flows off via the transistor M ₁ ; the potential at the connection point X ₁ therefore rises to "1" each time the clock pulse CP ₁ assumes the value "1".

₁ has the clock pulse CP is "0", the potential of the connection point X ₁ independently of the switching state of the transistor M ₁ is equal to "0". As a result, given an input _{pulse S 1,} an output pulse S _{2 is obtained} at the connection point X ₁ , as shown in FIG. 2D.

The output pulse Sp and the clock pulse CPp are fed to the transistor M, which goes into the conductive switching state when the clock pulse CP _{2 is} at the value "1". Therefore, if the output pulse S _{2 has} the value "1" and the transistor M is switched _{to the conductive switching state by the clock pulse CP 2} , the capacitance between the connection point X ₂ and the semiconductor substrate is reduced by the output pulse S _{2 of} the value "1"charged; accordingly, the connection point X ₂ is held at the value "1" by the charge. The charge stored in this way is charged via the transistor M, which is switched to the conductive switching state _{by the clock pulse CP 2 when the output pulse S 2 is} at the value "0". If the output pulse S _{2 has} the value "0", then the potential at the connection point X ₂ drops to "0" when the clock pulse CP ₂ rises to the value "1". At the connection point X _{2 there is} an output pulse S ,, as shown in FIG. 2E, which has the opposite phase to the input _{pulse S 1 and} lags behind the input _{pulse S 1} by the phase difference between the clock pulses CP ₁ and CP _2.

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The output pulse S _{i is applied to the circuit following the transistors M 1} to M i, which includes the transistors M 1 to M i in the same way as the previous stage. The clock pulses CP ₁ and CP ₂ in the second stage thus correspond to the clock pulses CP ₂ and CP. in the previous circuit stage. Is therefore obtained at the connection point X, a Ausgang3impuls S ^ (see. Figure 2f) corresponding to the output pulse S _2, while an output pulse (see. Fig. 2G) is present at the output terminal T _2, the opposite phase compared to the output pulse S , possesses and compared to this about the phase difference between the pulses CP ₂ and CP. lags, ie an output pulse Sc which is delayed by one cycle, ie by one time bit, _{with respect to the input pulse CP 1.}

The circuit according to Fig.l thus represents a delay flip-flop circuit It will be understood that a memory circuit can be constructed from a number of such circuits can be.

To build a memory circuit from such flip-flop circuits, for example four circuits of the type shown in Fig.l are produced on a single semiconductor substrate 2, as indicated in Fig.3 with la, Ib, Ic and Id. The flip-flop circuits la to Id are _{supplied with the clock pulses CP 1} and CP ₂ via common lines 3a and 3b. If the transistors M, the flip-flop circuits Ib and Ic, which fulfill different functions, are formed close to one another in the substrate 2, as shown in FIG. 1, a parasitic MIS transistor is formed.

As Figure 4 shows, the drain and source electrodes Db or Sb of the transistor M, of the flip-flop circuit Ib with P-type semiconductor layers in the N-semiconductor substrate 2.

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forms; an insulating layer Cb made of a relatively thin oxide film is provided over the electrodes Db and Sb; a gate electrode Gb is formed on the insulating layer Cb and completes the transistor M, des Flip-flop circle Ib.

In the same way, the transistor M of the flip-flop circuit Ic also contains a source electrode Sc and a drain electrode Dc, an insulating layer Cc and a gate Gc. In this case there is a relatively thick insulating layer Cp on the substrate 2 in the area between the insulating layers Cb and Cc; an inner connection line 3b on the insulating layer C ~ connects the gate electrodes Gb and Gc. The line 3b is supplied with the clock pulse CPp from the connection tp ( not shown in FIG. K).

As a result, a parasitic MIS transistor M is formed with the electrodes Sb and Sc, the insulating layer C_ and the inner lead 3b. FIG. 5 shows an equivalent circuit diagram of the semiconductor arrangement shown in FIGS. 3 and 4; a point Xb connected to the source electrode of the transistor M, of the flip-flop circuit Ib and a point Xc connected to the source electrode of the transistor M ^ of the flip-flop circuit Ic are connected via the drain and source of the parasitic transistor M tied together; the gate of the parasitic transistor M is connected to the terminal 1 _? tied together. As a result, when the value of the clock pulse CP _? a defined by the insulating layer C exceeds threshold _2, so is formed in the surface of the semiconductor substrate 2 under the insulating layer ₂ C an inverse layer, so that a channel between the electrodes Sb and Sc is produced. Therefore, if the value of the clock pulse CPp is higher than the threshold

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value voltage of the parasitic transistor M when the potential at one of the connection points Xb, Xc has the value "1" and the potential at the other connection point has the value "0", so the charge stored at the value "1" is discharged via the parasitic transistor M; one to be evaluated Signal is therefore lost, which results in incorrect puncture of the flip-flop circle.

An exemplary embodiment of the invention is now based on FIG Semiconductor described, which is formed so that a field-effect transistors with insulated gate built-up memory circuit does not receive any incorrect function due to a parasitic transistor. In Fig.6 are elements that correspond to those in Figure 4, provided with the same reference numerals.

According to the invention, the P-type semiconductor layer 5 is approximately in the middle between the source electrode Sb of the transistor M, the flip-flop circuit Ib and the source electrode Sc of the transistor M, the flip-flop circuit Ic in the N- Type semiconductor substrate 2 is formed so that a PN junction between the P-type semiconductor layer 5 and the N-type semiconductor substrate 2 is formed. For example, the P-type semiconductor layer 5 is formed simultaneously with the formation of the source and drain electrodes of each transistor. An electrode 4 is further provided on the P-type semiconductor layer 5. In the exemplary embodiment shown, the inner line 3b for supplying the clock pulse CPp is connected to the electrode 1J and thus connects the P-type semiconductor layer 5 to the source electrodes Sb and Sc of the transistors M ^1.

With such an arrangement, the clock pulse CPp. supplied to the P-type semiconductor layer 5 via the inner lead 3b; If the value of the clock pulse CPp exceeds the threshold voltage that is passed through the insulating layers C _{? h} and

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C _{0 is} determined. thus arise in the semiconductor substrate 2 under 2c

the insulating layers Cp. and Cp channels, ie between the electrode Sb and the semiconductor layer 5 and between the semiconductor layer 5 of the electrode Sc. However, even if the potential at the connection point Xb or Xc is "1", the voltage at the connection point Xb or Xc, that is, at the electrode Sb or Sc, never exceeds the value of the clock pulse CP ₃ . At the time when the clock pulse CP ″ is supplied, the charges stored at the connection points Xb and Xc are therefore not discharged through the channels into the semiconductor layer 5; this eliminates the possibility that the potentials at the connection points Xb and Xc, which should have the value "1", incorrectly assume the value "O".

On the other hand, there is no possibility that when the potential at the connection point Xb or Xc is "0", it is raised to "1" by the voltage taken from the semiconductor layer 5. FIG. 7 shows the equivalent circuit diagrams of the parasitic MIS transistors Mb and Mc, which in connection with the insulating layers C ₂ . and C ₂ and the transistors M, the flip-flop circuits Ib and Ic are formed; the drain electrode of the transistor M ^ is connected to the connection point Xb (Xc); the connection point Xb (Xc) is connected to the electrode 4 through the drain and source of the parasitic transistor Mb (Mc) and the gate of transistor Mb (Mc) is connected to the electrode ¹ I.

In this case, the insulating layer C _2b (Cp) for insulating the gate of the parasitic transistor Mb (Mc) is made thicker than for insulating the gate of the transistor M ₁ ; the steepness of the parasitic transistor Mb (Mc) is therefore smaller than that of the transistor M ..

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Therefore, even if the clock pulse CPp reaches the electrode H _{via the terminal t 2} , the voltage of the clock pulse CPp is divided by the transistors Mb (Mc) and M ₁ , so that only a very small voltage is present at the connection point Xb (Xc) . Thus, even if the value of the clock pulse CP _{2 is} higher than the threshold voltages of the parasitic transistors Mb and Mc, the value "O" of the potentials at the connection points Xb and Xc will not increase to the value "1" by an incorrect operation.

Preferably, therefore, the P-type semiconductor layer is im Center of the area in which the parasitic " see transistor forms.

The P-type semiconductor thickness is preferably smaller than the source and drain regions of the MIS transistor as they increases the degree of integration of the circuits and reduces the dimensions of the inner line for the clock pulse supply.

The invention provides an undesirable influence, in particular a false puncture through the parasitic MIS transistor is thus avoided, which is k formed by the inner conduit for the clock pulse supply in the semiconductor device, in the example a plurality of flip-flop circuits with MIS Transistors are provided on a semiconductor substrate to form a memory circuit. According to the invention, the thickness of the insulating layer under the inner line for the clock pulse supply can thus be selected independently of the voltage of the clock pulse .

In the above example, of course, the drain and source of the MIS transistor can be interchanged.

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Claims (2)

-ii- 20A7612 Claims ν 1.)) Semiconductor arrangement with a substrate of a conductivity type, an insulating layer formed on the substrate, a number of metal-insulated semiconductor transistors formed in the substrate, each having a source region and a drain region of the opposite conductivity type having substrate and a gate electrode on the insulating layer, further comprising an opening provided on the insulating layer for supplying a clock pulse to the transistors, characterized in that there is formed a diffusion region of opposite laws conductivity type wi _Eder substrate in the substrate and connected to the conductive layer . 2.) Semiconductor arrangement according to claim 1, characterized in that the area of the diffusion region is smaller than is that of the source region or the drain region. 109817/1298 Blank page