DE2033419A1 - Verfahren zum Herstellen von komplemen taren gitterisoherten Feldeffekttransis toren - Google Patents

Verfahren zum Herstellen von komplemen taren gitterisoherten Feldeffekttransis toren

Info

Publication number
DE2033419A1
DE2033419A1 DE19702033419 DE2033419A DE2033419A1 DE 2033419 A1 DE2033419 A1 DE 2033419A1 DE 19702033419 DE19702033419 DE 19702033419 DE 2033419 A DE2033419 A DE 2033419A DE 2033419 A1 DE2033419 A1 DE 2033419A1
Authority
DE
Germany
Prior art keywords
layer
pair
area
areas
delimited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702033419
Other languages
German (de)
English (en)
Inventor
Lawrence Aloysius Somer ville NJ Murray (V St A)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE2033419A1 publication Critical patent/DE2033419A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/03Diffusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/043Dual dielectric
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/053Field effect transistors fets
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/106Masks, special
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/126Power FETs
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/151Simultaneous diffusion

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE19702033419 1969-10-21 1970-07-06 Verfahren zum Herstellen von komplemen taren gitterisoherten Feldeffekttransis toren Pending DE2033419A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US86807169A 1969-10-21 1969-10-21

Publications (1)

Publication Number Publication Date
DE2033419A1 true DE2033419A1 (de) 1971-04-29

Family

ID=25351017

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702033419 Pending DE2033419A1 (de) 1969-10-21 1970-07-06 Verfahren zum Herstellen von komplemen taren gitterisoherten Feldeffekttransis toren

Country Status (6)

Country Link
US (1) US3700507A (enExample)
JP (1) JPS4911034B1 (enExample)
BE (1) BE753453A (enExample)
DE (1) DE2033419A1 (enExample)
FR (1) FR2064447B1 (enExample)
GB (1) GB1265932A (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3870576A (en) * 1970-04-29 1975-03-11 Ilya Leonidovich Isitovsky Method of making a profiled p-n junction in a plate of semiconductive material
US3892609A (en) * 1971-10-07 1975-07-01 Hughes Aircraft Co Production of mis integrated devices with high inversion voltage to threshold voltage ratios
JPS5321989B2 (enExample) * 1973-10-12 1978-07-06
JPS5286087A (en) * 1976-01-10 1977-07-16 Toshiba Corp Manufacture of semiconductor device
US4045259A (en) * 1976-10-26 1977-08-30 Harris Corporation Process for fabricating diffused complementary field effect transistors
US4345366A (en) * 1980-10-20 1982-08-24 Ncr Corporation Self-aligned all-n+ polysilicon CMOS process
US4462151A (en) * 1982-12-03 1984-07-31 International Business Machines Corporation Method of making high density complementary transistors
US4470191A (en) * 1982-12-09 1984-09-11 International Business Machines Corporation Process for making complementary transistors by sequential implantations using oxidation barrier masking layer
JPH0630355B2 (ja) * 1983-05-16 1994-04-20 ソニー株式会社 半導体装置
JPH01105529A (ja) * 1987-10-19 1989-04-24 Toshiba Corp 半導体装置の製造方法
US5116778A (en) * 1990-02-05 1992-05-26 Advanced Micro Devices, Inc. Dopant sources for cmos device
US6265256B1 (en) * 1998-09-17 2001-07-24 Advanced Micro Devices, Inc. MOS transistor with minimal overlap between gate and source/drain extensions

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1448383A (fr) * 1964-09-24 1966-08-05 Ibm Procédé de fabrication d'éléments semi-conducteurs

Also Published As

Publication number Publication date
FR2064447B1 (enExample) 1976-05-28
JPS4911034B1 (enExample) 1974-03-14
US3700507A (en) 1972-10-24
BE753453A (fr) 1970-12-16
GB1265932A (enExample) 1972-03-08
FR2064447A1 (enExample) 1971-07-23

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