DE19959966A1 - Verfahren zur Bildung von dielektrischen Schichten - Google Patents
Verfahren zur Bildung von dielektrischen SchichtenInfo
- Publication number
- DE19959966A1 DE19959966A1 DE19959966A DE19959966A DE19959966A1 DE 19959966 A1 DE19959966 A1 DE 19959966A1 DE 19959966 A DE19959966 A DE 19959966A DE 19959966 A DE19959966 A DE 19959966A DE 19959966 A1 DE19959966 A1 DE 19959966A1
- Authority
- DE
- Germany
- Prior art keywords
- dielectric layer
- hdpcvd
- conductive structures
- dielectric
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (16)
Bereitstellen eines Halbleitersubstrates;
Bilden von mehreren leitfähigen Strukturen über dem Halbleitersubstrat;
Bilden einer ersten dielektrischen Schicht auf und zwischen den leitfähigen Strukturen unter Verwendung eines ersten HDPCVD-Verfahrens, wobei die erste dielektrische Schicht eine gute Stufendeckfähigkeit aufweist;
Bilden einer zweiten dielektrischen Schicht auf der ersten dielektrischen Schicht unter Verwendung eines zweiten HDPCVD-Verfahrens, wobei mindestens ein Lufteinschluss in der zweiten dielektrischen Schicht zwischen den leitfähigen Strukturen gebildet wird;
und
Bilden einer dritten dielektrischen Schicht auf der zweiten dielektrischen Schicht unter Verwendung eines dritten HDPCVD-Verfahrens.
Bereitstellen von mehreren leitfähigen Strukturen;
Bilden einer konformen ersten dielektrischen Schicht auf und zwischen den leitfähigen Strukturen;
Bilden einer zweiten dielektrischen Schicht zwischen den leitfähigen Strukturen, wobei mindestens ein Lufteinschluss in der zweiten dielektrischen Schicht gebildet wird;
und
Bilden einer dritten dielektrischen Schicht auf der zweiten dielektrischen Schicht mit einer ebenen bzw. planen Oberfläche.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19959966A DE19959966C2 (de) | 1999-12-13 | 1999-12-13 | Verfahren zur Bildung von dielektrischen Schichten mit Lufteinschlüssen |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19959966A DE19959966C2 (de) | 1999-12-13 | 1999-12-13 | Verfahren zur Bildung von dielektrischen Schichten mit Lufteinschlüssen |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19959966A1 true DE19959966A1 (de) | 2001-06-28 |
DE19959966C2 DE19959966C2 (de) | 2003-09-11 |
Family
ID=7932413
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19959966A Expired - Fee Related DE19959966C2 (de) | 1999-12-13 | 1999-12-13 | Verfahren zur Bildung von dielektrischen Schichten mit Lufteinschlüssen |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE19959966C2 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10201178A1 (de) * | 2002-01-15 | 2003-06-26 | Infineon Technologies Ag | Verfahren zur Maskierung einer Ausnehmung einer Struktur mit einem großen Aspektverhältnis |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE6902266U (de) * | 1969-01-20 | 1969-08-21 | Burger Eisenwerke Ag Fa | Laugenbehaelter einer haushaltswaschmaschine |
DE19747559A1 (de) * | 1997-10-06 | 1999-05-06 | United Microelectronics Corp | Verbindungsstruktur mit Gasdielektrikum, das zum Durchlöchern ohne Kontaktfleck kompatibel ist |
US5936295A (en) * | 1994-05-27 | 1999-08-10 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
US5968610A (en) * | 1997-04-02 | 1999-10-19 | United Microelectronics Corp. | Multi-step high density plasma chemical vapor deposition process |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5013691A (en) * | 1989-07-31 | 1991-05-07 | At&T Bell Laboratories | Anisotropic deposition of silicon dioxide |
US5955786A (en) * | 1995-06-07 | 1999-09-21 | Advanced Micro Devices, Inc. | Semiconductor device using uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines |
US5776834A (en) * | 1995-06-07 | 1998-07-07 | Advanced Micro Devices, Inc. | Bias plasma deposition for selective low dielectric insulation |
-
1999
- 1999-12-13 DE DE19959966A patent/DE19959966C2/de not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE6902266U (de) * | 1969-01-20 | 1969-08-21 | Burger Eisenwerke Ag Fa | Laugenbehaelter einer haushaltswaschmaschine |
US5936295A (en) * | 1994-05-27 | 1999-08-10 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
US5968610A (en) * | 1997-04-02 | 1999-10-19 | United Microelectronics Corp. | Multi-step high density plasma chemical vapor deposition process |
DE19747559A1 (de) * | 1997-10-06 | 1999-05-06 | United Microelectronics Corp | Verbindungsstruktur mit Gasdielektrikum, das zum Durchlöchern ohne Kontaktfleck kompatibel ist |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10201178A1 (de) * | 2002-01-15 | 2003-06-26 | Infineon Technologies Ag | Verfahren zur Maskierung einer Ausnehmung einer Struktur mit einem großen Aspektverhältnis |
US7261829B2 (en) | 2002-01-15 | 2007-08-28 | Infineon Technologies Ag | Method for masking a recess in a structure having a high aspect ratio |
Also Published As
Publication number | Publication date |
---|---|
DE19959966C2 (de) | 2003-09-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8304 | Grant after examination procedure | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE Owner name: PROMOS TECHNOLOGIES, INC., HSINCHU, TW Owner name: MOSEL VITELIC INC., HSINCHU, TW |
|
R081 | Change of applicant/patentee |
Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNERS: MOSEL VITELIC INC., HSINCHU, TW; PROMOS TECHNOLOGIES, INC., HSINCHU, TW; QIMONDA AG, 81739 MUENCHEN, DE Owner name: MOSEL VITELIC INC., TW Free format text: FORMER OWNERS: MOSEL VITELIC INC., HSINCHU, TW; PROMOS TECHNOLOGIES, INC., HSINCHU, TW; QIMONDA AG, 81739 MUENCHEN, DE Owner name: PROMOS TECHNOLOGIES, INC., TW Free format text: FORMER OWNERS: MOSEL VITELIC INC., HSINCHU, TW; PROMOS TECHNOLOGIES, INC., HSINCHU, TW; QIMONDA AG, 81739 MUENCHEN, DE Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: MOSEL VITELIC INC., PROMOS TECHNOLOGIES, INC., QIMONDA AG, , TW Owner name: MOSEL VITELIC INC., TW Free format text: FORMER OWNER: MOSEL VITELIC INC., PROMOS TECHNOLOGIES, INC., QIMONDA AG, , TW Owner name: PROMOS TECHNOLOGIES, INC., TW Free format text: FORMER OWNER: MOSEL VITELIC INC., PROMOS TECHNOLOGIES, INC., QIMONDA AG, , TW |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |