DE19921113C2 - Verfahren zur COB-Montage von elektronischen Chips auf einer Schaltungsplatine - Google Patents
Verfahren zur COB-Montage von elektronischen Chips auf einer SchaltungsplatineInfo
- Publication number
- DE19921113C2 DE19921113C2 DE19921113A DE19921113A DE19921113C2 DE 19921113 C2 DE19921113 C2 DE 19921113C2 DE 19921113 A DE19921113 A DE 19921113A DE 19921113 A DE19921113 A DE 19921113A DE 19921113 C2 DE19921113 C2 DE 19921113C2
- Authority
- DE
- Germany
- Prior art keywords
- chip
- circuit board
- adhesive
- partial bonding
- connecting wires
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 25
- 239000000853 adhesive Substances 0.000 claims description 21
- 230000001070 adhesive effect Effects 0.000 claims description 21
- 238000004026 adhesive bonding Methods 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 239000002390 adhesive tape Substances 0.000 claims description 4
- 229920001169 thermoplastic Polymers 0.000 claims description 4
- 239000004416 thermosoftening plastic Substances 0.000 claims description 4
- 239000012790 adhesive layer Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Die Bonding (AREA)
Description
Claims (6)
- - Teilverklebung des Chips (2) auf der Schaltungspla tine (1) in der Weise, daß der Chip (2) kontaktiert werden kann und ohne Beschädigung der Schaltungs platine wieder entfernbar ist, wobei die Teilver klebung zumindest in dem den Kontaktflächen des Chips gegenüberliegenden Bereich des Chips (2) er folgt,
- - Durchführung elektronischer Tests oder Programmie rungen an dem Chip oder Modul (2), sowie
- - Vollverklebung des Chips (2) bei gegebener Funkti onsfähigkeit in einer für die Anwendung der Schal tungsplatine erforderlichen Weise.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19921113A DE19921113C2 (de) | 1999-05-07 | 1999-05-07 | Verfahren zur COB-Montage von elektronischen Chips auf einer Schaltungsplatine |
US09/566,936 US6312962B1 (en) | 1999-05-07 | 2000-05-08 | Method for COB mounting of electronic chips on a circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19921113A DE19921113C2 (de) | 1999-05-07 | 1999-05-07 | Verfahren zur COB-Montage von elektronischen Chips auf einer Schaltungsplatine |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19921113A1 DE19921113A1 (de) | 2000-11-30 |
DE19921113C2 true DE19921113C2 (de) | 2001-11-22 |
Family
ID=7907322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19921113A Expired - Fee Related DE19921113C2 (de) | 1999-05-07 | 1999-05-07 | Verfahren zur COB-Montage von elektronischen Chips auf einer Schaltungsplatine |
Country Status (2)
Country | Link |
---|---|
US (1) | US6312962B1 (de) |
DE (1) | DE19921113C2 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10133361C2 (de) | 2001-07-10 | 2003-05-28 | Infineon Technologies Ag | Verfahren zur Herstellung einer Verpackung für Halbleiterchips |
KR100771860B1 (ko) | 2004-12-28 | 2007-11-01 | 삼성전자주식회사 | 솔더볼을 사용하지 않는 반도체 패키지 모듈 및 그 제조방법 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4232404A1 (de) * | 1992-09-26 | 1994-03-31 | Diehl Gmbh & Co | Verfahren zum Testen eines integrierten Schaltungs-Chips |
DE4338248A1 (de) * | 1993-11-09 | 1995-05-11 | Siemens Ag | Vorrichtung zum Testen einer Lead-on-Chip-Verbindung |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04171969A (ja) * | 1990-11-06 | 1992-06-19 | Fujitsu Ltd | 実装icチップ樹脂封止構造及び樹脂封止方法 |
US5169056A (en) * | 1992-02-21 | 1992-12-08 | Eastman Kodak Company | Connecting of semiconductor chips to circuit substrates |
-
1999
- 1999-05-07 DE DE19921113A patent/DE19921113C2/de not_active Expired - Fee Related
-
2000
- 2000-05-08 US US09/566,936 patent/US6312962B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4232404A1 (de) * | 1992-09-26 | 1994-03-31 | Diehl Gmbh & Co | Verfahren zum Testen eines integrierten Schaltungs-Chips |
DE4338248A1 (de) * | 1993-11-09 | 1995-05-11 | Siemens Ag | Vorrichtung zum Testen einer Lead-on-Chip-Verbindung |
Non-Patent Citations (1)
Title |
---|
LANG, OSTERWALD, REICHL: Erfolgreiche Übergangslösung, Warum immer mehr Schaltungs- entwickler auf Chip-on-Board setzen, In: F&M 106 (1998), 12, Carl Hanser Verlag, München, S. 908-912 * |
Also Published As
Publication number | Publication date |
---|---|
DE19921113A1 (de) | 2000-11-30 |
US6312962B1 (en) | 2001-11-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8127 | New person/name/address of the applicant |
Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE |
|
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE |
|
R081 | Change of applicant/patentee |
Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE |
|
R081 | Change of applicant/patentee |
Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |