DE1956501C3 - Integrierte Schaltungsanordnung - Google Patents

Integrierte Schaltungsanordnung

Info

Publication number
DE1956501C3
DE1956501C3 DE1956501A DE1956501A DE1956501C3 DE 1956501 C3 DE1956501 C3 DE 1956501C3 DE 1956501 A DE1956501 A DE 1956501A DE 1956501 A DE1956501 A DE 1956501A DE 1956501 C3 DE1956501 C3 DE 1956501C3
Authority
DE
Germany
Prior art keywords
silicon chip
integrated circuit
circuit arrangement
connecting conductors
plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE1956501A
Other languages
German (de)
English (en)
Other versions
DE1956501A1 (de
DE1956501B2 (de
Inventor
Claudio Dr. Ivrea Torino Dalmasso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TIM SpA
Original Assignee
Ing C Olivetti and C SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ing C Olivetti and C SpA filed Critical Ing C Olivetti and C SpA
Publication of DE1956501A1 publication Critical patent/DE1956501A1/de
Publication of DE1956501B2 publication Critical patent/DE1956501B2/de
Application granted granted Critical
Publication of DE1956501C3 publication Critical patent/DE1956501C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/435—Shapes or dispositions of insulating layers on leadframes, e.g. bridging members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/124—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed the encapsulations having cavities other than that occupied by chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/811—Multiple chips on leadframes

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
  • Bipolar Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Casings For Electric Apparatus (AREA)
  • Combinations Of Printed Boards (AREA)
DE1956501A 1968-11-06 1969-11-05 Integrierte Schaltungsanordnung Expired DE1956501C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT5375968 1968-11-06

Publications (3)

Publication Number Publication Date
DE1956501A1 DE1956501A1 (de) 1970-06-11
DE1956501B2 DE1956501B2 (de) 1980-06-04
DE1956501C3 true DE1956501C3 (de) 1983-04-07

Family

ID=11285001

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1956501A Expired DE1956501C3 (de) 1968-11-06 1969-11-05 Integrierte Schaltungsanordnung

Country Status (11)

Country Link
US (1) US3673309A (https=)
JP (1) JPS493230B1 (https=)
BE (1) BE741287A (https=)
CA (1) CA924021A (https=)
CH (1) CH526203A (https=)
DE (1) DE1956501C3 (https=)
FR (1) FR2022698B1 (https=)
GB (2) GB1288982A (https=)
NL (1) NL6916792A (https=)
SE (1) SE362166B (https=)
SU (1) SU462366A3 (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3872583A (en) * 1972-07-10 1975-03-25 Amdahl Corp LSI chip package and method
GB2079534A (en) * 1980-07-02 1982-01-20 Fairchild Camera Instr Co Package for semiconductor devices
DE3512628A1 (de) * 1984-04-11 1985-10-17 Moran, Peter, Cork Packung fuer eine integrierte schaltung
JPS6132452A (ja) * 1984-07-25 1986-02-15 Hitachi Ltd リ−ドフレ−ムとそれを用いた電子装置
US4809135A (en) * 1986-08-04 1989-02-28 General Electric Company Chip carrier and method of fabrication
US4791075A (en) * 1987-10-05 1988-12-13 Motorola, Inc. Process for making a hermetic low cost pin grid array package
US5061822A (en) * 1988-09-12 1991-10-29 Honeywell Inc. Radial solution to chip carrier pitch deviation
US5122621A (en) * 1990-05-07 1992-06-16 Synergy Microwave Corporation Universal surface mount package
US5160810A (en) * 1990-05-07 1992-11-03 Synergy Microwave Corporation Universal surface mount package
US5229329A (en) * 1991-02-28 1993-07-20 Texas Instruments, Incorporated Method of manufacturing insulated lead frame for integrated circuits
US5403784A (en) * 1991-09-03 1995-04-04 Microelectronics And Computer Technology Corporation Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template
DE4225154A1 (de) * 1992-07-30 1994-02-03 Meyerhoff Dieter Chip-Modul
JP3619085B2 (ja) * 1999-02-18 2005-02-09 キヤノン株式会社 画像形成装置、その製造方法及び記憶媒体
US8212351B1 (en) * 2006-10-02 2012-07-03 Newport Fab, Llc Structure for encapsulating microelectronic devices
RU2331138C1 (ru) * 2006-12-26 2008-08-10 Закрытое акционерное общество "Научно-производственное объединение "НИИТАЛ" (ЗАО "НПО "НИИТАЛ") Корпус интегральной схемы
US8309388B2 (en) * 2008-04-25 2012-11-13 Texas Instruments Incorporated MEMS package having formed metal lid
WO2019075289A1 (en) * 2017-10-13 2019-04-18 Kulicke And Soffa Industries, Inc. CONDUCTIVE TERMINALS, OMNIBUS BARS, AND METHODS OF PREPARING THE SAME, AND METHODS OF ASSEMBLING POWER MODULES THEREOF
CN110854080B (zh) * 2019-11-26 2021-10-19 合肥圣达电子科技实业有限公司 一种多引线陶瓷组件封装外壳及其加工方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3331125A (en) * 1964-05-28 1967-07-18 Rca Corp Semiconductor device fabrication
US3312771A (en) * 1964-08-07 1967-04-04 Nat Beryllia Corp Microelectronic package
US3374437A (en) * 1964-08-26 1968-03-19 Heath Co Squelch system for radio receivers
US3374537A (en) * 1965-03-22 1968-03-26 Philco Ford Corp Method of connecting leads to a semiconductive device
US3317653A (en) * 1965-05-07 1967-05-02 Cts Corp Electrical component and method of making the same
US3371148A (en) * 1966-04-12 1968-02-27 Radiation Inc Semiconductor device package and method of assembly therefor
US3404215A (en) * 1966-04-14 1968-10-01 Sprague Electric Co Hermetically sealed electronic module
US3560256A (en) * 1966-10-06 1971-02-02 Western Electric Co Combined thick and thin film circuits
US3469148A (en) * 1967-11-08 1969-09-23 Gen Motors Corp Protectively covered hybrid microcircuits
US3495023A (en) * 1968-06-14 1970-02-10 Nat Beryllia Corp Flat pack having a beryllia base and an alumina ring

Also Published As

Publication number Publication date
DE1956501A1 (de) 1970-06-11
DE1956501B2 (de) 1980-06-04
JPS493230B1 (https=) 1974-01-25
CH526203A (it) 1972-07-31
BE741287A (https=) 1970-05-05
SU462366A3 (ru) 1975-02-28
US3673309A (en) 1972-06-27
GB1288982A (https=) 1972-09-13
GB1288983A (https=) 1972-09-13
CA924021A (en) 1973-04-03
NL6916792A (https=) 1970-05-11
FR2022698A1 (https=) 1970-08-06
SE362166B (https=) 1973-11-26
FR2022698B1 (https=) 1975-11-07

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Legal Events

Date Code Title Description
SH Request for examination between 03.10.1968 and 22.04.1971
8381 Inventor (new situation)

Free format text: DALMASSO, CLAUDIO, DR., IVREA, TORINO, IT

C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee