DE1923325A1 - Verfahren zum Herstellen einer Verbundhalbleiteranordnung - Google Patents

Verfahren zum Herstellen einer Verbundhalbleiteranordnung

Info

Publication number
DE1923325A1
DE1923325A1 DE19691923325 DE1923325A DE1923325A1 DE 1923325 A1 DE1923325 A1 DE 1923325A1 DE 19691923325 DE19691923325 DE 19691923325 DE 1923325 A DE1923325 A DE 1923325A DE 1923325 A1 DE1923325 A1 DE 1923325A1
Authority
DE
Germany
Prior art keywords
semiconductor
trench
crystal
semiconductor components
surface zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19691923325
Other languages
German (de)
English (en)
Inventor
Reindl Dipl-Ing Klaus
Johansen Dipl-Chem Jon Willy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE19691923325 priority Critical patent/DE1923325A1/de
Priority to NL7006123A priority patent/NL7006123A/xx
Priority to CH664370A priority patent/CH506189A/de
Priority to AT406070A priority patent/AT323805B/de
Priority to FR7016335A priority patent/FR2042448B1/fr
Priority to GB1297404D priority patent/GB1297404A/en
Priority to SE637770A priority patent/SE356399B/xx
Publication of DE1923325A1 publication Critical patent/DE1923325A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE19691923325 1969-05-07 1969-05-07 Verfahren zum Herstellen einer Verbundhalbleiteranordnung Pending DE1923325A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE19691923325 DE1923325A1 (de) 1969-05-07 1969-05-07 Verfahren zum Herstellen einer Verbundhalbleiteranordnung
NL7006123A NL7006123A (enrdf_load_stackoverflow) 1969-05-07 1970-04-27
CH664370A CH506189A (de) 1969-05-07 1970-05-04 Verfahren zum Herstellen einer monolithischen, integrierten Schaltung
AT406070A AT323805B (de) 1969-05-07 1970-05-05 Verfahren zur herstellung von isolierten bereichen bei einer verbundhalbleiteranordnung
FR7016335A FR2042448B1 (enrdf_load_stackoverflow) 1969-05-07 1970-05-05
GB1297404D GB1297404A (enrdf_load_stackoverflow) 1969-05-07 1970-05-06
SE637770A SE356399B (enrdf_load_stackoverflow) 1969-05-07 1970-05-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19691923325 DE1923325A1 (de) 1969-05-07 1969-05-07 Verfahren zum Herstellen einer Verbundhalbleiteranordnung

Publications (1)

Publication Number Publication Date
DE1923325A1 true DE1923325A1 (de) 1970-11-19

Family

ID=5733514

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19691923325 Pending DE1923325A1 (de) 1969-05-07 1969-05-07 Verfahren zum Herstellen einer Verbundhalbleiteranordnung

Country Status (7)

Country Link
AT (1) AT323805B (enrdf_load_stackoverflow)
CH (1) CH506189A (enrdf_load_stackoverflow)
DE (1) DE1923325A1 (enrdf_load_stackoverflow)
FR (1) FR2042448B1 (enrdf_load_stackoverflow)
GB (1) GB1297404A (enrdf_load_stackoverflow)
NL (1) NL7006123A (enrdf_load_stackoverflow)
SE (1) SE356399B (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
CH506189A (de) 1971-04-15
FR2042448B1 (enrdf_load_stackoverflow) 1975-01-10
SE356399B (enrdf_load_stackoverflow) 1973-05-21
NL7006123A (enrdf_load_stackoverflow) 1970-11-10
GB1297404A (enrdf_load_stackoverflow) 1972-11-22
FR2042448A1 (enrdf_load_stackoverflow) 1971-02-12
AT323805B (de) 1975-07-25

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