DE1621532B2 - Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe - Google Patents

Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe

Info

Publication number
DE1621532B2
DE1621532B2 DE19671621532 DE1621532A DE1621532B2 DE 1621532 B2 DE1621532 B2 DE 1621532B2 DE 19671621532 DE19671621532 DE 19671621532 DE 1621532 A DE1621532 A DE 1621532A DE 1621532 B2 DE1621532 B2 DE 1621532B2
Authority
DE
Germany
Prior art keywords
etching
etched
mask
solution
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19671621532
Other languages
German (de)
English (en)
Other versions
DE1621532A1 (de
Inventor
Roger Clyde Bethlehem Waggener Herbert Atkin Allentown Pa Kragness (V St A)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE1621532A1 publication Critical patent/DE1621532A1/de
Publication of DE1621532B2 publication Critical patent/DE1621532B2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/764Air gaps
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/32Alkaline compositions
    • C23F1/40Alkaline compositions for etching other metallic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30608Anisotropic liquid etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Mechanical Engineering (AREA)
  • Materials Engineering (AREA)
  • Weting (AREA)
DE19671621532 1966-12-20 1967-12-19 Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe Withdrawn DE1621532B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US60329266A 1966-12-20 1966-12-20

Publications (2)

Publication Number Publication Date
DE1621532A1 DE1621532A1 (de) 1970-10-22
DE1621532B2 true DE1621532B2 (de) 1971-10-07

Family

ID=24414811

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19671621532 Withdrawn DE1621532B2 (de) 1966-12-20 1967-12-19 Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe

Country Status (7)

Country Link
BE (1) BE708163A (enrdf_load_stackoverflow)
DE (1) DE1621532B2 (enrdf_load_stackoverflow)
FR (1) FR1548079A (enrdf_load_stackoverflow)
GB (1) GB1212379A (enrdf_load_stackoverflow)
MY (1) MY7300447A (enrdf_load_stackoverflow)
NL (1) NL144778B (enrdf_load_stackoverflow)
SE (1) SE342526B (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226451A3 (en) * 1985-12-13 1989-08-23 Xerox Corporation Sensor arrays

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3844858A (en) * 1968-12-31 1974-10-29 Texas Instruments Inc Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate
GB1288278A (enrdf_load_stackoverflow) * 1968-12-31 1972-09-06
US3579057A (en) * 1969-08-18 1971-05-18 Rca Corp Method of making a semiconductor article and the article produced thereby
CA957782A (en) * 1970-01-26 1974-11-12 Theodore Kamprath Capacitor structure for integrated circuits
DE2106540A1 (de) * 1970-02-13 1971-08-19 Texas Instruments Inc Halbleiterschaltung und Verfahren zu ihrer Herstellung
DE3879771D1 (de) * 1987-05-27 1993-05-06 Siemens Ag Aetzverfahren zum erzeugen von lochoeffnungen oder graeben in n-dotiertem silizium.
GB9204078D0 (en) * 1992-02-26 1992-04-08 Philips Electronics Uk Ltd Infrared detector manufacture
US5508231A (en) * 1994-03-07 1996-04-16 National Semiconductor Corporation Apparatus and method for achieving mechanical and thermal isolation of portions of integrated monolithic circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226451A3 (en) * 1985-12-13 1989-08-23 Xerox Corporation Sensor arrays

Also Published As

Publication number Publication date
GB1212379A (en) 1970-11-18
MY7300447A (en) 1973-12-31
NL6716390A (enrdf_load_stackoverflow) 1968-06-21
FR1548079A (enrdf_load_stackoverflow) 1968-11-29
NL144778B (nl) 1975-01-15
DE1621532A1 (de) 1970-10-22
BE708163A (enrdf_load_stackoverflow) 1968-05-02
SE342526B (enrdf_load_stackoverflow) 1972-02-07

Similar Documents

Publication Publication Date Title
EP0001100B1 (de) Verfahren zum Herstellen von in Silicium eingelegten dielektrischen Isolationsbereichen mittels geladener und beschleunigter Teilchen
EP0000897B1 (de) Verfahren zum Herstellen von lateral isolierten Siliciumbereichen
DE2303798C2 (de) Verfahren zum Herstellen von Halbleiterbauelementen
DE3224604C2 (enrdf_load_stackoverflow)
DE2928923C2 (enrdf_load_stackoverflow)
DE2644939A1 (de) Aetzverfahren zum abflachen eines siliciumsubstrats
DE1439741C3 (de) Verfahren zur Herstellung einer Festkörperschaltung mit geringer Nebenschlußkapazität
DE2738008A1 (de) Verfahren zum herstellen einer eintransistor-speicherzelle
DE2238450C3 (de) Verfahren zur Herstellung einer integrierten Halbleiteranordnung
DE1564191B2 (de) Verfahren zum herstellen einer integrierten halbleiterschaltung mit verschiedenen, gegeneinander und gegen ein gemeinsames siliziumsubstrat elektrisch isolierten schaltungselementen
DE2328090C2 (de) Verfahren zur Herstellung eines Halbleiterkondensators
DE2615754C2 (enrdf_load_stackoverflow)
DE1963162C3 (de) Verfahren zur Herstellung mehrerer Halbleiterbauelemente aus einer einkristallinen Halbleiterscheibe
DE1621532B2 (de) Verfahren zum herstellen formgebender einaetzungen an einer monokristallinen halbleiterscheibe
DE2633714C2 (de) Integrierte Halbleiter-Schaltungsanordnung mit einem bipolaren Transistor und Verfahren zu ihrer Herstellung
DE2409910B2 (de) Verfahren zum Herstellen einer Halbleiteranordnung
DE2239687C3 (de) Verfahren zum Ätzen eines mehrschichtigen Halbleiterkörpers mit einem flüssigen Ätzmittel
DE1965406A1 (de) Monolithische integrierte Schaltungen und Verfahren zu ihrer Herstellung
DE1018558B (de) Verfahren zur Herstellung von Richtleitern, Transistoren u. dgl. aus einem Halbleiter
DE1589920A1 (de) Verfahren zum gegenseitigen elektrischen Isolieren verschiedener in einer integrierten oder monolithischen Halbleitervorrichtung zusammengefasster Schaltelemente
DE1953665A1 (de) Verfahren zum oertlichen anisotropen AEtzen eines Siliciumkoerpers und Halbleiterbauelement mit einem auf diese Weise geaetzten Siliciumkoerper
DE1965408C3 (de) Verfahren zum Herstellen eines Halbleiterbauelementes
DE1621532C (de) Verfahren zum Herstellen formgebender Einätzungen an einer monokristallinen Halbleiterscheibe
DE1280416B (de) Verfahren zum Herstellen epitaktischer Halbleiterschichten auf elektrisch leitenden Schichten
DE2100292A1 (de) Halbleiteranordnung mit relativ kleinen geometrischen Abmessungen und Verfahren zur Herstellung derselben

Legal Events

Date Code Title Description
E77 Valid patent as to the heymanns-index 1977
8339 Ceased/non-payment of the annual fee