DE1514683B1 - Verfahren zum Erzeugen von elektrischen Nebenschluessen zum UEberbruecken von pn-UEbergaengen in Halbleiterkoerpern - Google Patents

Verfahren zum Erzeugen von elektrischen Nebenschluessen zum UEberbruecken von pn-UEbergaengen in Halbleiterkoerpern

Info

Publication number
DE1514683B1
DE1514683B1 DE19661514683 DE1514683A DE1514683B1 DE 1514683 B1 DE1514683 B1 DE 1514683B1 DE 19661514683 DE19661514683 DE 19661514683 DE 1514683 A DE1514683 A DE 1514683A DE 1514683 B1 DE1514683 B1 DE 1514683B1
Authority
DE
Germany
Prior art keywords
semiconductor
mask
semiconductor body
perforated
perforations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19661514683
Other languages
German (de)
English (en)
Inventor
Kurt Dr Rer Nat Raithel
Rene Rosenheinrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of DE1514683B1 publication Critical patent/DE1514683B1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/106Masks, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
DE19661514683 1966-02-12 1966-02-12 Verfahren zum Erzeugen von elektrischen Nebenschluessen zum UEberbruecken von pn-UEbergaengen in Halbleiterkoerpern Pending DE1514683B1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DES0101984 1966-02-12

Publications (1)

Publication Number Publication Date
DE1514683B1 true DE1514683B1 (de) 1970-04-02

Family

ID=7524118

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19661514683 Pending DE1514683B1 (de) 1966-02-12 1966-02-12 Verfahren zum Erzeugen von elektrischen Nebenschluessen zum UEberbruecken von pn-UEbergaengen in Halbleiterkoerpern

Country Status (8)

Country Link
US (1) US3589937A (US07655688-20100202-C00109.png)
BE (1) BE693884A (US07655688-20100202-C00109.png)
CH (1) CH450556A (US07655688-20100202-C00109.png)
DE (1) DE1514683B1 (US07655688-20100202-C00109.png)
FR (1) FR1511259A (US07655688-20100202-C00109.png)
GB (1) GB1107497A (US07655688-20100202-C00109.png)
NL (1) NL6701904A (US07655688-20100202-C00109.png)
SE (1) SE319838B (US07655688-20100202-C00109.png)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079406A (en) * 1974-08-13 1978-03-14 Siemens Aktiengesellschaft Thyristor having a plurality of emitter shorts in defined spacial relationship
DE3744308A1 (de) * 1987-12-28 1989-07-06 Bbc Brown Boveri & Cie Leistungshalbleiter-bauelement sowie verfahren zu dessen herstellung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE966879C (de) * 1953-02-21 1957-09-12 Standard Elektrik Ag Verfahren zur Reinigung und/oder Abtragung von Halbleitermaterial, insbesondere von Germanium- und Siliziumsubstanz
DE1132405B (de) * 1960-11-04 1962-06-28 Siemens Ag Verfahren zum lokalisierten AEtzen der Oberflaeche von Werkstuecken, insbesondere von Halbleiterkristallen
DE1152293B (de) * 1958-08-12 1963-08-01 Siemens Ag Verfahren zum oertlich begrenzten AEtzen von pn-UEbergaengen benachbarten Flaechen an Halbleiterkoerpern von elektrischen Halbleiteranordnungen

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE966879C (de) * 1953-02-21 1957-09-12 Standard Elektrik Ag Verfahren zur Reinigung und/oder Abtragung von Halbleitermaterial, insbesondere von Germanium- und Siliziumsubstanz
DE1152293B (de) * 1958-08-12 1963-08-01 Siemens Ag Verfahren zum oertlich begrenzten AEtzen von pn-UEbergaengen benachbarten Flaechen an Halbleiterkoerpern von elektrischen Halbleiteranordnungen
DE1132405B (de) * 1960-11-04 1962-06-28 Siemens Ag Verfahren zum lokalisierten AEtzen der Oberflaeche von Werkstuecken, insbesondere von Halbleiterkristallen

Also Published As

Publication number Publication date
BE693884A (US07655688-20100202-C00109.png) 1967-08-09
CH450556A (de) 1968-01-31
US3589937A (en) 1971-06-29
NL6701904A (US07655688-20100202-C00109.png) 1967-08-14
FR1511259A (fr) 1968-01-26
SE319838B (US07655688-20100202-C00109.png) 1970-01-26
GB1107497A (en) 1968-03-27

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