DE1158292B - Schaltungsanordnung zur Addition binaerer Signale - Google Patents

Schaltungsanordnung zur Addition binaerer Signale

Info

Publication number
DE1158292B
DE1158292B DER30909A DER0030909A DE1158292B DE 1158292 B DE1158292 B DE 1158292B DE R30909 A DER30909 A DE R30909A DE R0030909 A DER0030909 A DE R0030909A DE 1158292 B DE1158292 B DE 1158292B
Authority
DE
Germany
Prior art keywords
transistor
circuit
negative resistance
tunnel diode
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DER30909A
Other languages
German (de)
English (en)
Inventor
Juan Jose Amodei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE1158292B publication Critical patent/DE1158292B/de
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5013—Half or full adders, i.e. basic adder cells for one denomination using algebraic addition of the input signals, e.g. Kirchhoff adders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/10—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using tunnel diodes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4828—Negative resistance devices, e.g. tunnel diodes, gunn effect devices

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Algebra (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
DER30909A 1960-08-22 1961-08-10 Schaltungsanordnung zur Addition binaerer Signale Pending DE1158292B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5094660A 1960-08-22 1960-08-22

Publications (1)

Publication Number Publication Date
DE1158292B true DE1158292B (de) 1963-11-28

Family

ID=21968488

Family Applications (1)

Application Number Title Priority Date Filing Date
DER30909A Pending DE1158292B (de) 1960-08-22 1961-08-10 Schaltungsanordnung zur Addition binaerer Signale

Country Status (3)

Country Link
DE (1) DE1158292B (enExample)
GB (1) GB957101A (enExample)
NL (1) NL268446A (enExample)

Also Published As

Publication number Publication date
GB957101A (en) 1964-05-06
NL268446A (enExample)

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