DE112023005602T5 - Halbleitereinrichtung und Verfahren zum Herstellen einer Halbleitereinrichtung - Google Patents

Halbleitereinrichtung und Verfahren zum Herstellen einer Halbleitereinrichtung

Info

Publication number
DE112023005602T5
DE112023005602T5 DE112023005602.1T DE112023005602T DE112023005602T5 DE 112023005602 T5 DE112023005602 T5 DE 112023005602T5 DE 112023005602 T DE112023005602 T DE 112023005602T DE 112023005602 T5 DE112023005602 T5 DE 112023005602T5
Authority
DE
Germany
Prior art keywords
gate
trench
area
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112023005602.1T
Other languages
German (de)
English (en)
Inventor
Toshiaki Iwamatsu
Akihiro Koyama
Takeshi Kitani
Tomokatsu Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE112023005602T5 publication Critical patent/DE112023005602T5/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE112023005602.1T 2023-01-12 2023-01-12 Halbleitereinrichtung und Verfahren zum Herstellen einer Halbleitereinrichtung Pending DE112023005602T5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2023/000592 WO2024150368A1 (ja) 2023-01-12 2023-01-12 半導体装置、および、半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE112023005602T5 true DE112023005602T5 (de) 2025-11-13

Family

ID=91896554

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112023005602.1T Pending DE112023005602T5 (de) 2023-01-12 2023-01-12 Halbleitereinrichtung und Verfahren zum Herstellen einer Halbleitereinrichtung

Country Status (4)

Country Link
JP (1) JP7851428B2 (https=)
CN (1) CN120457788A (https=)
DE (1) DE112023005602T5 (https=)
WO (1) WO2024150368A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN121548078B (zh) * 2026-01-19 2026-04-14 广东芯粤能半导体有限公司 集成鳍式结构的元胞结构及其制备方法、SiC功率器件

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007088010A (ja) * 2005-09-20 2007-04-05 Denso Corp 半導体装置およびその製造方法
WO2013076890A1 (ja) * 2011-11-21 2013-05-30 パナソニック株式会社 半導体装置及びその製造方法
JP5790573B2 (ja) * 2012-04-03 2015-10-07 株式会社デンソー 炭化珪素半導体装置およびその製造方法
JP6848317B2 (ja) * 2016-10-05 2021-03-24 富士電機株式会社 半導体装置および半導体装置の製造方法
JP7196463B2 (ja) * 2018-08-23 2022-12-27 富士電機株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
JP7331653B2 (ja) * 2019-11-19 2023-08-23 株式会社デンソー 半導体装置の製造方法
JP2021136313A (ja) * 2020-02-26 2021-09-13 株式会社日立製作所 半導体装置およびその製造方法

Also Published As

Publication number Publication date
WO2024150368A1 (ja) 2024-07-18
JPWO2024150368A1 (https=) 2024-07-18
JP7851428B2 (ja) 2026-04-24
CN120457788A (zh) 2025-08-08

Similar Documents

Publication Publication Date Title
EP1303883B1 (de) Halbleiteraufbau mit vergrabenem inselgebiet und kontaktgebiet
DE112016003510B4 (de) HALBLEITERVORRlCHTUNG UND VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERVORRICHTUNG
DE112015004515B4 (de) Halbleitervorrichtungen
DE112013002518B4 (de) Halbleiterbauteil und Verfahren zu dessen Herstellung
DE102008024464B4 (de) Halbleitervorrichtung
DE102011052731B4 (de) Verfahren zum Bilden einer Feldeffekt-Leistungshalbleitervorrichtung und Feldeffekt-Halbleitervorrichtung mit einer integrierten Polydiode
DE112015004766B4 (de) Halbleitervorrichtungen
DE102019216309B4 (de) Siliciumcarbid-halbleitervorrichtung und verfahren zur herstellung einer siliciumcarbid-halbleitervorrichtung
DE112017004237B4 (de) Halbleitereinheit
DE112014003489B4 (de) Siliciumcarbid-Halbleitervorrichtung und Verfahren zum Herstellen derselben
DE102015107331B4 (de) Halbleitervorrichtung und rückwärts leitender Bipolartransistor mit isoliertem Gate mit isolierten Sourcezonen
DE102021116586B4 (de) Halbleitervorrichtung
DE112015006403T5 (de) Siliciumcarbid-halbleitereinheit und verfahren zur herstellung derselben
DE102010036743A1 (de) Bipolares Halbleiterbauelement und Herstellungsverfahren
DE102019216131A1 (de) Halbleitervorrichtung
DE112016004718T5 (de) Halbleitereinheit
DE102021127759A1 (de) Halbleitervorrichtung und Halbleitereinrichtung
DE102020122641B4 (de) Halbleitervorrichtung
DE112018008178T5 (de) Halbleitereinheit
DE112017002113T5 (de) Halbleitereinheit
DE102019131060A1 (de) Halbleitergerät
DE112022006775T5 (de) Halbleitereinrichtung und Herstellungsverfahren für eine Halbleitereinrichtung
DE112014004599T5 (de) Siliziumkarbid-Halbleitervorrichtung
DE102009044670B4 (de) Bipolares Halbleiterbauelement und Herstellungsverfahren
DE102018120432B4 (de) Leistungshalbleitervorrichtung mit zulässig verifizierbarem p-Kontakt und Verfahren

Legal Events

Date Code Title Description
R012 Request for examination validly filed