WO2024150368A1 - 半導体装置、および、半導体装置の製造方法 - Google Patents

半導体装置、および、半導体装置の製造方法 Download PDF

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Publication number
WO2024150368A1
WO2024150368A1 PCT/JP2023/000592 JP2023000592W WO2024150368A1 WO 2024150368 A1 WO2024150368 A1 WO 2024150368A1 JP 2023000592 W JP2023000592 W JP 2023000592W WO 2024150368 A1 WO2024150368 A1 WO 2024150368A1
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Prior art keywords
trench
region
gate
semiconductor device
insulating film
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PCT/JP2023/000592
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English (en)
French (fr)
Japanese (ja)
Inventor
俊明 岩松
皓洋 小山
剛 木谷
友勝 渡辺
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to PCT/JP2023/000592 priority Critical patent/WO2024150368A1/ja
Priority to JP2024569941A priority patent/JP7851428B2/ja
Priority to DE112023005602.1T priority patent/DE112023005602T5/de
Priority to CN202380089855.3A priority patent/CN120457788A/zh
Publication of WO2024150368A1 publication Critical patent/WO2024150368A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • the technology disclosed in this specification relates to semiconductor technology.
  • insulated gate semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) are widely used as switching elements that control the power supply to loads such as motors.
  • MOSFETs Metal Oxide Semiconductor Field Effect Transistors
  • IGBTs Insulated Gate Bipolar Transistors
  • Insulated gate semiconductor devices have a trench structure in which the gate electrode is embedded in the semiconductor layer.
  • Insulated gate semiconductor devices with a trench structure can increase the channel width density of the active region compared to insulated gate semiconductor devices (planar type semiconductor devices) that do not have a trench structure in which the gate electrode is formed on the surface of the semiconductor layer. This makes it possible to reduce the electrical resistance per unit area when the semiconductor device is in the on state.
  • insulated gate semiconductor devices with a trench structure, a gate electrode and a gate insulating film are formed inside the trench and around the upper corners of the trench opening on the active region side in a termination region provided around the active region.
  • an electric field concentrates around the bottom surface of the trench and the upper corners, causing insulation deterioration of the gate insulating film around the bottom surface of the trench and the upper corners.
  • the reliability of the semiconductor device may decrease.
  • a method in which a structure is formed with a narrow, deep trench in the active region and a wide, shallow trench in the termination region, and then a CMP (Chemical Mechanical Polishing) process or a combination of the CMP process and an etch-back process is used to planarize the gate electrodes formed in the trenches in the active region and termination region, thereby preventing the upper corners of the trench from being covered by the gate electrodes (see, for example, Patent Document 2).
  • CMP Chemical Mechanical Polishing
  • the gate contact may be set on the top surface of the polysilicon in a wide trench in the termination region.
  • the method of providing an electric field relaxation region at the bottom of the trench may not be able to suppress insulation deterioration around the upper corners of the trench.
  • the method using the CMP process requires extremely small effects such as warping of the semiconductor substrate, unevenness of the substrate surface, uniformity of the in-plane thickness of the film formed on the semiconductor substrate, and unevenness of the film due to the effects of particles, etc., making it difficult to adopt in practice.
  • the exposed area of the gate electrode becomes large in the subsequent etch-back process, and the gate electrode may be etched to a thinner thickness, or may disappear. This may cause the operation of the insulated gate semiconductor device to become unstable (reliability of the semiconductor device to decrease). Also, it may not be possible to suppress insulation deterioration around the upper corners of the trench.
  • the technology disclosed in this specification was developed in consideration of the problems described above, and is a technology for suppressing deterioration in the reliability of insulated gate semiconductor devices having a trench structure.
  • a semiconductor device includes a drift layer of a first conductivity type, a base region of a second conductivity type provided on a surface layer of the drift layer, a plurality of source regions of the first conductivity type provided on a surface layer of the base region, at least one trench extending from an upper surface of the drift layer through the base region into the drift layer, a protective layer of the second conductivity type provided in the drift layer below the trench, a gate insulating film provided along the inside of the trench including the upper corners of the trench, and a gate insulating film surrounding at least the trench.
  • the semiconductor device further includes a gate electrode provided within the trench, a source electrode electrically connected to the source region adjacent to the trench, and a gate wiring provided on the upper surface of the gate electrode provided within the trench, and among the regions separated by the trench in a plan view, the region in which the source electrode is provided is defined as a first region, and the region in which the gate wiring is provided is defined as a second region, and the radius of curvature of the gate insulating film provided at the upper corner of the trench in the second region is larger than the radius of curvature of the gate insulating film provided at the upper corner of the trench in the first region.
  • electric field concentration is suppressed even when a gate voltage is applied, thereby suppressing breakdown of the gate insulating film.
  • 1 is a plan view illustrating an example of a configuration of a semiconductor device according to an embodiment.
  • 1 is a cross-sectional view showing a part of a configuration of a semiconductor device according to an embodiment
  • 1 is a cross-sectional view showing a part of a configuration of a semiconductor device according to an embodiment
  • 1 is a plan view showing a part of a configuration of a semiconductor device according to an embodiment
  • FIG. 2 is a cross-sectional view showing an example of the configuration of the cell portion in the figure.
  • 4 is a cross-sectional view showing an example of the configuration of a gate contact portion in the active region 20 of FIG. 3.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1 is a plan view illustrating an example of a configuration of a semiconductor device according to an embodiment of the present invention.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1 is a plan view illustrating an example of a configuration of a semiconductor device according to an embodiment of the present invention.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment.
  • 1 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to an embodiment.
  • 1 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to an embodiment.
  • 1 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to an embodiment.
  • 1 is a cross-sectional view illustrating an example of a configuration of a semiconductor device according to an embodiment.
  • 1 is a cross-sectional view illustrating an example of a configuration of a semiconductor
  • the upper surface of " or “the lower surface of " when it is stated that “the upper surface of " or “the lower surface of " is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component.
  • the upper surface of " or “the lower surface of " when it is stated that "B is provided on the upper surface of A,” it does not prevent another component "C" from being interposed between A and B.
  • ⁇ Configuration of Semiconductor Device> 1 is a plan view showing a schematic configuration example of a semiconductor device 100 according to the present embodiment. As shown in the example of FIG. 1, the semiconductor device 100 includes an active region 20 and a termination region 30.
  • the active region 20 has a plurality of gate trenches 6 arranged in a plan view.
  • the termination region 30 has a termination trench 16 and a gate wiring 18 formed so as to overlap the termination trench 16 in a plan view.
  • a gate trench 26 is formed in the inner portion of the termination region 30.
  • the active region 20 is provided in the center of the semiconductor device 100.
  • the active region 20 is a region that passes current through the semiconductor device 100 when a voltage is applied to the gate trenches 6 formed in a stripe shape within the active region 20.
  • the termination region 30 is formed around the active region 20 in a plan view.
  • the termination region 30 has a termination trench 16, a gate insulating film 17, a gate electrode 8, a gate wiring 18, and a guard ring for the purpose of alleviating the electric field.
  • the termination trench 16 is a trench provided in the termination region 30.
  • the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the semiconductor device may also have a first conductivity type of p-type and a second conductivity type of n-type.
  • the semiconductor device is described as a MOSFET, but the semiconductor device may be an IGBT.
  • the drift layer included in the semiconductor layer is described as being formed of silicon carbide (SiC), but the drift layer may be a wide bandgap semiconductor with a larger bandgap than silicon, such as gallium nitride (GaN) or diamond.
  • a gate trench 6 is formed in the active region 20, and a gate trench 26 and a termination trench 16 are formed in the termination region 30.
  • the termination trench 16 surrounds the gate trench 6 and the gate trench 26 in a plan view, and is formed at a distance from the gate trench 6 and the gate trench 26.
  • the gate trenches 6 are formed in a stripe shape in plan view.
  • a plurality of cells (cell portions) are formed in each area partitioned by the gate trenches 6 in the active region 20, and the cells function as MOSFETs.
  • FIGS. 2 and 3 are cross-sectional views showing a part of the configuration of a semiconductor device according to this embodiment.
  • FIG. 4 is a plan view showing a part of the configuration of a semiconductor device according to this embodiment.
  • the configurations shown in FIGS. 2, 3, and 4 correspond to the area 1000 surrounded by the dashed line in FIG. 1.
  • the cross section shown in FIG. 2 corresponds to the A-A' cross section shown in FIG. 4.
  • the cross section shown in FIG. 3 corresponds to the B-B' cross section shown in FIG. 4.
  • the semiconductor device 100 which is a MOSFET, comprises an n-type silicon carbide semiconductor substrate 1 and a semiconductor layer 2 formed by epitaxial growth on the upper surface of the silicon carbide semiconductor substrate 1.
  • the semiconductor device 100 also comprises a drain electrode 12 on the lower surface of the silicon carbide semiconductor substrate 1.
  • a drift layer 3 made of an n-type silicon carbide semiconductor, a p-type base region 4 provided on the surface of the drift layer 3, an n-type source region 5 selectively provided on the surface of the base region 4, a gate trench 6 formed to penetrate the source region 5 and the base region 4 and have its bottom surface located within the drift layer 3, and a p-type diffusion protection layer 9 provided below the bottom surface of the gate trench 6 are formed.
  • the conductivity type of the silicon carbide semiconductor substrate 1 should be p-type.
  • drift layer 3 may have an n-type impurity concentration of, for example, 1 ⁇ 10 14 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less, and drift layer 3 may have a thickness of, for example, 5 ⁇ m or more and 200 ⁇ m or less.
  • the p-type impurity concentration of base region 4 may be, for example, not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the n-type impurity concentration of the source region 5 may be equal to or higher than the p-type impurity concentration of the base region 4 and equal to or lower than 1 ⁇ 10 21 cm ⁇ 3 .
  • the p-type impurity concentration of the diffusion protection layer 9 and the p-type impurity concentration of the termination protection layer 19 may be, for example, not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 19 cm ⁇ 3 .
  • the p-type impurity concentration of the diffusion protection layer 9 is preferably the same as or not less than the p-type impurity concentration of the termination protection layer 19.
  • a gate insulating film 7 is formed on the side and bottom of the gate trench 6, and a gate electrode 8 made of polysilicon is embedded in the gate trench 6 via the gate insulating film 7.
  • the gate insulating film 7 and gate electrode 8 in the gate trench 6 that overlap with the gate wiring 18 in a planar view are formed to extend to the upper surface of the semiconductor layer 2 (the upper surface of the semiconductor layer 2 on which the base region 4 or the source region 5 is formed).
  • a gate insulating film 7 of the same thickness as the gate insulating film 7 in the gate trench 6 is formed on the side and bottom surfaces of the gate trench 26, and a gate electrode 8 made of polysilicon is embedded in the gate trench 26 via the gate insulating film 7.
  • the gate electrode 8 in the gate trench 26 is formed up to the upper surface of the semiconductor layer 2.
  • the gate wiring 18 is provided across the upper surfaces of the gate electrodes 8 provided in the multiple gate trenches 6.
  • the polysilicon formed to extend to the upper surface of the semiconductor layer 2 has a gate electrode 8 formed through a contact hole (gate contact 34).
  • the gate electrode 8 extends to a bonding pad for wire bonding connection when the chip is assembled.
  • an electrically non-functional gate trench 26 is formed at the boundary between the termination region 30 and the active region 20.
  • a termination trench 16 is formed that is wider than the gate trenches 6 and 26, and a gate insulating film 7 of the same thickness as the gate insulating film 7 in the gate trench 6 is formed on the bottom and side surfaces of the termination trench 16.
  • An interlayer insulating film 13 (oxide film) is deposited in a portion of the termination trench 16.
  • a gate electrode 8 is formed in another portion of the termination trench 16.
  • a gate electrode 8 is formed in the gate trench 6 of the cell section.
  • Polysilicon (gate electrode 8) is also deposited in the gate trench 26 at the boundary between the termination region 30 and the active region 20.
  • an interlayer insulating film 13 is formed to cover the upper surface of the semiconductor layer 2 including the gate electrode 8.
  • a gate wiring 18 is formed so as to contact the gate electrode 8 exposed through a gate contact 34, which is an opening formed in the interlayer insulating film 13.
  • the gate contact 34 is classified into two types: one that exposes the gate electrode 8 in the termination trench 16 in the termination region 30, and one that exposes the gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2 in the active region 20.
  • a source electrode 11 is formed so as to contact, via an ohmic electrode 32, the upper surface of the base region 4 and the upper surface of the source region 5 exposed through a source contact 31, which is an opening formed in the interlayer insulating film 13.
  • An oxide film (interlayer insulating film 13) is formed in the termination trench 16 in the termination region 30, while polysilicon is formed in the gate trench 6 and the gate trench 26, meaning that different materials are formed in the two regions.
  • the gate trench 6 or gate trench 26 in the cell section is formed with the minimum processing line width. Because there is a difference in structure between the two, the thermal history in the wafer process causes the expansion coefficients of the materials to differ. This causes residual stress, which results in differences in the electrical characteristics of the elements and also affects the reliability of the semiconductor device.
  • FIG. 5 is a cross-sectional view showing an example of the configuration of the cell portion in FIG. 2. As shown in the example in FIG. 5, the upper corners of the gate trench 6 are rounded.
  • FIG. 6 is a cross-sectional view showing an example of the configuration of the gate contact portion in the active region 20 of FIG. 3. As shown in the example in FIG. 6, the upper corners of the gate trench 6 have a rounded shape.
  • the upper corner of the semiconductor layer 2 in the cell portion where the gate electrode 8 is embedded in the gate trench 6 has a rounded shape indicated by the radius of curvature Rc. Therefore, the shape of the gate insulating film 7 formed in that portion is also rounded indicated by the radius of curvature Rc.
  • the upper corner of the semiconductor layer 2 of the gate contact portion having the gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2 has a rounded shape indicated by the radius of curvature Re. Therefore, the shape of the gate insulating film 7 formed in that portion is also rounded indicated by the radius of curvature Re.
  • the gate contact portion Comparing the radii of curvature of the gate trench 6 directly below the gate insulating film 7, Re>Rc, and the gate contact portion has a gentler shape.
  • the small radius of curvature Rc of the cell portion is, for example, greater than 0 ⁇ m and equal to or less than 0.1 ⁇ m.
  • the radius of curvature Re of the gate contact portion is, for example, equal to or greater than 0.1 ⁇ m and equal to or less than 2 ⁇ m. In particular, if the radius of curvature Re of the gate contact portion is equal to or greater than 0.5 ⁇ m and equal to or less than 2 ⁇ m, good characteristics can be obtained.
  • a gate insulating film 7 and a gate electrode 8 are formed at the upper corners of the gate trench 6 in the gate contact section. Since the radius of curvature Re is larger than the radius of curvature Rc, it is possible to prevent a high electric field from being applied to the gate insulating film 7 formed at the upper corners of the gate trench 6 when the MOSFET is turned on.
  • the gate contact portion is formed with a gate insulating film 7 having a curvature radius Re, it is possible to prevent a high electric field from being applied to the gate insulating film 7 formed in the upper corner of the gate trench 6, thereby preventing the insulating film from breaking down.
  • the radius of curvature Re so as to suppress the electric field applied to the gate insulating film 7 near the gate trench 6, which has the radius of curvature Re, to an increment of 5% or less.
  • the gate contact portion shown in FIG. 6 is assumed to be provided in the active region 20, but the upper corners of the termination trench 16 at the gate contact portion in the termination region 30 (where the gate wiring 18 and the gate electrode 8 are connected via the gate contact 34) may be rounded.
  • the source electrode and the ohmic electrode may not be distinguished from each other and may be collectively referred to as the source electrode.
  • the gate bonding pad and the ohmic electrode may not be distinguished from each other and may be collectively referred to as the gate bonding pad.
  • the source electrode and the gate bonding pad are not limited to being made of a single metal, but may be configured such that a material suitable for bonding with the semiconductor layer is provided at the junction with the semiconductor layer.
  • the ohmic electrode is not limited to a metal, but may be a compound of a metal and a semiconductor, or a silicide.
  • the ohmic electrode may be configured to be made of multiple layers of metal or a conductor such as a semiconductor.
  • Figures 7 to 18 are diagrams showing an example of a method for manufacturing a semiconductor device according to this embodiment.
  • FIGS. 7 to 11 show examples of the process for forming the diffusion protection layer 9 below the bottom surface of the gate trench 6 and the termination protection layer 19 below the bottom surface of the termination trench 16. Note that FIGS. 7 to 10 correspond to the A-A' cross section of FIG. 11.
  • FIGS. 12 to 15 show an example of the process from forming the diffusion protection layer 9 and the termination protection layer 19 to forming the gate electrode 8. Note that FIG. 12 and FIG. 13 correspond to the A-A' cross section of FIG. 15. Also, FIG. 14 corresponds to the B-B' cross section of FIG. 15.
  • FIGS. 16 to 18 show an example of the process from forming the gate electrode 8 to completing the semiconductor device 100.
  • an n-type silicon carbide semiconductor substrate 1 having a polytype of 4H is prepared, and an n-type semiconductor layer 2 is epitaxially grown on the upper surface of the substrate by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the n-type impurity concentration of the n-type semiconductor layer 2 is, for example, 1 ⁇ 10 14 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less, and the thickness of the semiconductor layer 2 is, for example, 5 ⁇ m or more and 200 ⁇ m or less.
  • Al (Al) as a p-type impurity is ion-implanted into the surface layer of the epitaxially grown semiconductor layer 2 to form a base region 4.
  • the depth of Al ion implantation is set within a range not exceeding the thickness of the semiconductor layer 2, for example, 0.3 ⁇ m or more and 3 ⁇ m or less.
  • the impurity concentration of Al ion-implanted is set higher than the n-type impurity concentration of the epitaxially grown semiconductor layer 2, and the p-type impurity concentration of the base region 4 is set, for example, 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the region of the semiconductor layer 2 other than the base region 4 deeper than the ion implantation depth of Al becomes an n-type drift layer 3.
  • the base region 4 may be formed by epitaxially growing a p-type semiconductor, in which case the p-type impurity concentration and thickness of the base region 4 may be the same as when the base region 4 is formed by ion implantation.
  • N nitrogen (N), which is an n-type impurity, is selectively ion-implanted into the surface layer of the base region 4 to form the source region 5.
  • the source region 5 is formed in a pattern corresponding to the layout of the gate electrode 8 to be formed in a later process.
  • the depth of N ion implantation is made shallower than the thickness of the base region 4.
  • the impurity concentration of N ion-implanted is set to be equal to or greater than the p-type impurity concentration of the base region 4 and equal to or less than 1 ⁇ 10 21 cm -3 .
  • the order of the process of ion implanting Al to form the base region 4 and the process of ion implanting N to form the source region 5 may be reversed.
  • the portion to be left as the source region 5 may be masked, and Al may be ion implanted again into the unmasked region (region other than the source region 5) to return to the p-type base region 4.
  • the impurity concentration of the re-ion implanted Al may be made higher than the impurity concentration of Al in the base region 4 adjacent to the drift layer 3 to reduce the contact resistance with the source electrode.
  • a silicon oxide film 41 is formed on the upper surface of the semiconductor layer 2, and an etching mask 42 is further formed on the upper surface of the silicon oxide film 41.
  • the silicon oxide film 41 is formed by deposition to a thickness of, for example, 1 ⁇ m or more and 2 ⁇ m or less, and then the etching mask 42 is formed on the upper surface of the silicon oxide film 41.
  • a pattern having openings corresponding to the regions where the gate trench 6, the gate trench 26, and the termination trench 16 are to be formed is formed in the etching mask 42 by photolithography technology.
  • RIE reactive ion etching
  • the patterned silicon oxide film 41 is used as a mask to form gate trenches 6 and 26 that penetrate the source region 5 and base region 4 in the semiconductor layer 2, and a termination trench 16 that penetrates the base region 4 in the RIE process.
  • the depth of the gate trench 6, the gate trench 26 and the termination trench 16 is equal to or greater than the depth of the base region 4 formed by ion implantation in the semiconductor layer 2, and may be, for example, 1.0 ⁇ m or more and 6.0 ⁇ m or less.
  • the gate trench 6, the gate trench 26, and the termination trench 16 are formed. Then, after the gate trench 6, the gate trench 26, and the termination trench 16 are formed, as shown in FIG. 10, an implantation mask 43 having an opening of the same pattern as the silicon oxide film 41 is formed, and a p-type diffusion protection layer 9 is formed at the bottom of the gate trench 6 and the bottom of the gate trench 26 by ion implantation of Al. Similarly, a p-type termination protection layer 19 is formed at the bottom of the termination trench 16 by ion implantation of Al.
  • the impurity concentration of Al to be ion-implanted is, for example, 1 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less, and the depth of the ion implantation is preferably, for example, 0.1 ⁇ m or more and 2.0 ⁇ m or less.
  • the impurity concentration of Al to be ion-implanted may be determined based on the electric field applied to the gate insulating film 7 when a voltage equal to the breakdown voltage of the semiconductor device 100 is applied between the drain electrode 12 and the source electrode 11 of the semiconductor device 100.
  • the remaining silicon oxide film 41 can be used as a mask instead of the implantation mask 43 when forming the diffusion protection layer 9 and the termination protection layer 19. This makes it possible to simplify the manufacturing process and reduce manufacturing costs.
  • the diffusion protection layer 9 Al ions are implanted obliquely into the opening of the gate trench 6, forming a p-type semiconductor layer in the drift layer 3 that contacts the side surface of the gate trench 6, and the p-type diffusion protection layer 9 and the p-type base region 4 can be connected by the p-type semiconductor layer. This allows the diffusion protection layer 9 and the source electrode 11 to be electrically connected.
  • the implantation mask 43 used for the ion implantation is removed, and an annealing process is performed to activate the implanted impurities using a heat treatment device.
  • the annealing process is performed by heating in an inert gas atmosphere such as argon (Ar) or in a vacuum at a temperature of 1300°C or higher and 1900°C or lower for 30 seconds or longer and 1 hour or shorter.
  • the implantation mask 43 is removed and the upper surface of the semiconductor layer 2 is oxidized.
  • the thickness of the oxide film formed on the upper surface of the semiconductor layer 2 is preferably, for example, 5 nm or more and 100 nm or less.
  • the oxide film is then removed by hydrofluoric acid-based wet etching. This process forms a round shape (radius of curvature Rc) at the upper corners of each trench.
  • an oxide film 41A is deposited, and then, as shown in FIG. 14, only the portion of the oxide film 41A corresponding to the area where the gate contact of the active region 20 is to be formed is opened.
  • the oxide film 41A is etched to expose a portion of the semiconductor layer 2, and a round shape (radius of curvature Re) is formed at the upper corner of the gate trench 6 in the exposed semiconductor layer 2.
  • a round shape radius of curvature Re
  • the rounded shape can be formed by CDE (chemical dry etching: isotropic etching) etching or other etching processes (such as heat treatment in a hydrogen atmosphere). After that, the oxide film 41A is removed.
  • CDE chemical dry etching: isotropic etching
  • the upper corners of the trench which were rounded (with radius of curvature Rc) in the process shown in FIG. 12, can be further heat-treated in a CDE or hydrogen atmosphere in the process shown in FIG. 14 to form a rounded shape with an even larger radius of curvature at the upper corners of the gate trench 6.
  • the radius of curvature Re of the gate insulating film 7 provided at the upper corner of the gate trench 6 (or the termination trench 16) in the region where the gate wiring 18 is provided on the upper surface is larger than the radius of curvature Rc of the gate insulating film 7 provided at the upper corner of the gate trench 6 in the region where the source electrode 11 is electrically connected to the adjacent source region 5.
  • FIG. 16 corresponds to the A-A' cross section of FIG. 18.
  • FIG. 17 corresponds to the B-B' cross section of FIG. 18.
  • a gate insulating film 7 and a gate electrode 8 are formed in the gate trench 6, the gate trench 26, and the termination trench 16, respectively.
  • polysilicon that will become the gate electrode 8 is deposited.
  • the deposited polysilicon is then etched back using resist as a mask. As a result, the polysilicon is etched back in areas where there is no resist, and polysilicon is formed in the gate trench 6, the gate trench 26, and the termination trench 16.
  • the region covered with the resist is a region in which a round shape (radius of curvature Re) is formed at the upper corner of the gate trench 6, and the polysilicon is not etched back, and polysilicon remains in the mesa region (upper surface of the semiconductor layer 2).
  • the upper corner of the gate trench 6 has a large round shape (radius of curvature Re)
  • the interlayer insulating film 13 is formed on the upper surface of the semiconductor layer 2 by low pressure CVD so as to cover the gate electrode 8. Then, the interlayer insulating film 13 is patterned to form contact holes (gate contacts 34) in the active region 20 and the termination region 30 that reach the source region 5 and the base region 4. Also, a contact hole (source contact 31) is formed in the active region that reaches the gate electrode 8. After that, an ohmic electrode 25 is formed in the gate contact 34 (see FIG. 6). Also, an ohmic electrode 32 is formed in the source contact 31.
  • Each ohmic electrode may be a silicide film formed by forming a metal film mainly composed of nickel (Ni) on the upper surface of the semiconductor layer 2 and the upper surface of the gate electrode 8, and then reacting Ni with the semiconductor by heat treatment at, for example, 600° C. or more and 1100° C. or less.
  • Ni nickel
  • an Al alloy or the like is deposited on the upper surface of the interlayer insulating film 13, in the gate contact 34, and in the source contact 31, and then patterned to form the gate wiring 18 via the gate contact 34 and the source electrode 11 via the source contact 31.
  • the semiconductor device 100 is formed.
  • the voltage applied between the gate electrode 8 and the source electrode 11 is controlled to control the channel formed in the base region 4 facing the gate electrode 8 via the gate insulating film 7, thereby controlling the on and off states of the semiconductor device 100.
  • a voltage large enough to turn on the semiconductor device 100 is applied between the gate electrode 8 and the source electrode 11, a voltage equal to or greater than the threshold is applied to the gate electrode 8.
  • a channel is formed in the base region 4 facing the gate electrode 8 via the gate insulating film 7, and a path through which electrons, which are carriers, flow is formed between the n-type source region 5 and the n-type drift layer 3.
  • a high voltage supplied from an external electric circuit is applied between the drain electrode 12 and the source electrode 11.
  • a depletion layer spreads from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3, which prevents the electric field caused by the voltage applied between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 at the bottom of the gate trench 6, and prevents breakdown even if a high electric field is applied to the gate insulating film 7 at the bottom of the gate trench 6.
  • the gate insulating film 7 when the semiconductor device 100 is turned on, a voltage supplied from an external electric circuit is applied between the gate electrode 8 and the source electrode 11. The application of the voltage applies an electric field to the gate insulating film 7. Because the upper corners of the semiconductor layer 2 in the gate trench 6 are formed in a round shape with a radius of curvature Re, the gate insulating film 7 also has a rounded shape with a radius of curvature Re. This prevents the electric field caused by the voltage applied between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 at the upper corners of the gate trench 6, and prevents the gate insulating film 7 from being destroyed even when an electric field is applied to it.
  • the semiconductor device 100 when the semiconductor device 100 is in the on state, a current flows from the drain electrode 12 to the source electrode 11 due to a voltage supplied from an external electric circuit, and the voltage between the drain electrode 12 and the source electrode 11 becomes an on voltage, which is a voltage determined by the current flowing from the drain electrode 12 to the source electrode 11 and the on resistance of the semiconductor device 100.
  • the on voltage is much lower than the voltage applied between the drain electrode 12 and the source electrode 11 in the off state. Therefore, the depletion layer that spreads from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 in the off state shrinks toward the diffusion protection layer 9 and the termination protection layer 19 when the semiconductor device is in the on state.
  • the depletion layer that extends from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 expands and contracts as the semiconductor device 100 switches between the on and off states.
  • the semiconductor device 100 functions by repeatedly switching between the off state and the on state, but even the repeated on and off state operation applies voltage stress to the gate insulating film 7, accelerating deterioration. Since the upper corner of the semiconductor layer 2 in the gate trench 6 is formed in a round shape with a radius of curvature Re, the gate insulating film 7 at that location also has a rounded shape with a radius of curvature Re. This makes it possible to prevent the electric field between the drain electrode 12 and the source electrode 11 from concentrating on the gate insulating film 7 at the upper corner of the semiconductor layer 2. This makes it possible to suppress the acceleration of deterioration of the gate insulating film 7 and prevent its destruction.
  • an electrically non-functional gate trench 26 is formed at the boundary between the termination region 30 and the active region 20.
  • the termination region 30 and the active region 20 differ in both their stacked structure and processing dimensions in the direction along the silicon carbide semiconductor substrate 1.
  • residual stress occurs at the boundary, affecting electrical characteristics and causing destruction of the gate insulating film 7.
  • the failure rate of the gate insulating film 7 increases as it approaches the outermost periphery. For this reason, the outermost cell (corresponding to the gate trench 26) is electrically isolated from the other cells as the termination region 30, and its gate electrode 8 is not electrically connected to the source electrode 11 and the gate wiring 18, so that the gate potential is made floating, thereby preventing element destruction.
  • the yield rate of the gate trenches 26 shown in FIG. 4 increases as the number of gate trenches 26 increases. In other words, the quality of the semiconductor device 100 increases by forming multiple gate trenches 26.
  • Second Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described.
  • components similar to those described in the above embodiment are illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • ⁇ Configuration of Semiconductor Device> 19 is a plan view showing an example of the configuration of a semiconductor device 101 according to this embodiment. As shown in the example of FIG. 19, the semiconductor device 101 includes an active region 20 and a termination region 30.
  • the active region 20 there are formed a plurality of gate trenches 6 arranged in a plan view, a gate electrode 8 formed in the gate trench 6, and a gate wiring 18 connected to the gate electrode 8 via a gate contact 34.
  • the gate contact 34 is formed directly below the gate wiring 18 and directly above the gate electrode 8.
  • the gate electrode 8 is connected to a gate bonding pad 58 located on the periphery of the chip.
  • the gate bonding pad 58 and the gate electrode 8 are metal layers such as aluminum, and are formed in the same process.
  • a source electrode 11 is formed on the upper surface of the source region 5 formed on the surface layer of the semiconductor layer 2.
  • the source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31).
  • the source electrode 11 also extends to the source bonding pad 59.
  • a termination trench 16 and a gate wiring 18 are formed in a portion of the termination trench 16.
  • a metal wiring 120 is formed on the upper surface of the gate wiring 18 via a gate contact 34.
  • the metal wiring 120 is formed in the same process as the gate electrode 8 and the source electrode 11. Since the metal wiring 120 and the gate wiring 18 are formed in parallel connection, the electrical resistance can be reduced.
  • the semiconductor device 101 is configured as described above.
  • FIGS. 20 to 22 are diagrams showing an example of a method for manufacturing a semiconductor device according to this embodiment.
  • FIG. 20 corresponds to the plan view of the structure shown in FIG. 10.
  • Gate trenches 6 are formed in the active region 20, and outermost gate trenches 26 and termination trenches 16 are formed in the termination region 30.
  • Gate wiring 18 is formed in the gate trench 6 in the active region 20. Gate wiring 18 is also formed in the gate trench 26 in the termination region 30. Furthermore, gate wiring 18 is formed in a portion of the termination trench 16.
  • the gate wiring 18 is formed by depositing polysilicon in the gate trench 6, and then forming a mask of resist or the like in some areas and etching back the polysilicon.
  • Regions 108 and 109 indicated by dashed lines in FIG. 21 are regions where the polysilicon is not etched back due to the placement of the mask, and polysilicon remains on the upper surface of the semiconductor layer 2.
  • the polysilicon in these regions is not only formed within the gate trench 6, but also covers the upper corners of the gate trench 6 and is also formed in the mesa region (upper surface of the semiconductor layer 2).
  • the radius of curvature Re of the upper corners of the gate trench 6 is large, which can suppress the concentration of the electric field. This prevents the gate insulating film 7 from being destroyed.
  • the gate electrode 8 formed in the gate trench 26 in the termination region 30 and the gate electrode 8 formed in the gate trenches 6 arranged in a stripe pattern in the center of the active region 20 are separated in a plan view.
  • the gate wiring 18 is formed by etching back the deposited polysilicon.
  • FIG. 22 is a plan view showing an example of a structure in which an interlayer insulating film 13 is formed and a source contact 31 and a gate contact 34 are formed after the process shown in FIG. 21.
  • gate contacts 34 are formed on the upper surfaces of gate electrodes 8 in regions 108 and 109.
  • gate contacts 34 and gate wiring 18 can be formed in positions that overlap gate trenches 6 arranged in a stripe pattern in a plan view, so there is no need to provide a separate region for forming gate contacts 34. This allows the chip area to be reduced, and increases the freedom of design layout.
  • gate wiring 18 is formed in region 108 and connected to gate bonding pad 58.
  • metal wiring 120 is electrically connected to gate electrode 8 via a contact hole (gate contact 34).
  • Gate electrode 8 in termination region 30 extends to directly below gate bonding pad 58, and is electrically connected to gate electrode 8 via gate contact 34 in gate bonding pad 58.
  • the gate electrode 8 in the gate trench 6 in the cell array is electrically connected to the gate bonding pad 58 via the gate contact 34 in the center of the active region 20, and is also electrically connected to the gate electrode 8 formed in the termination region 30, the aluminum layer (metal wiring 120), and other gate electrodes 8 in the active region 20. This reduces the resistance of the gate electrode 8 in the gate trench 6 in the active region 20, resulting in good electrical characteristics (switching characteristics, on-characteristics).
  • the radius of curvature Re of the upper corners of the gate trench 6 in the region 108 at the center of the active region 20 where the gate contact 34 is formed is made large. Therefore, even when a gate voltage is applied during device operation, the concentration of the electric field at the upper corners of the gate trench 6 can be suppressed, and the destruction of the gate insulating film 7 can be suppressed.
  • ⁇ Configuration of Semiconductor Device> 23 is a plan view showing an example of the configuration of a semiconductor device 102 according to the present embodiment. As shown in the example of FIG. 23, the semiconductor device 102 includes an active region 20 and a termination region 30.
  • the active region 20 there are formed a plurality of gate trenches 6 arranged in a plan view, a gate electrode 8 formed in the gate trench 6, and a gate wiring 18 connected to the gate electrode 8 via a gate contact 34.
  • the gate contact 34 is formed directly below the gate wiring 18 and in the upper layer of the gate electrode 8.
  • the gate electrode 8 is connected to a gate bonding pad 58 located on the periphery of the chip.
  • the gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum, and are formed in the same process.
  • a source electrode 11 is formed on the upper surface of the source region 5 formed on the surface layer of the semiconductor layer 2.
  • the source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31).
  • the source electrode 11 also extends to the source bonding pad 59.
  • a termination trench 16 and a gate electrode 8 are formed in a portion of the termination trench 16.
  • a metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34.
  • the metal wiring 122 is formed in the same process as the gate wiring 18 and the source electrode 11. Since the metal wiring 122 and the gate electrode 8 are formed in parallel connection, the gate resistance can be reduced.
  • the semiconductor device 102 is configured as described above.
  • FIGS. 24 and 25 are diagrams showing an example of a method for manufacturing a semiconductor device according to this embodiment.
  • FIG. 24 corresponds to the plan view of the structure shown in FIG. 16.
  • a gate electrode 8 is formed in the gate trench 6 in the active region 20.
  • a gate electrode 8 is also formed in the gate trench 26 in the termination region 30. Furthermore, a gate electrode 8 is formed in a partial region of the termination trench 16.
  • the gate electrode 8 is formed by depositing polysilicon in the gate trench 6, and then forming a mask of resist or the like in some areas and etching back the polysilicon.
  • Regions 108 and 109 indicated by dashed lines in FIG. 24 are regions where the polysilicon is not etched back due to the placement of the mask, and polysilicon remains on the upper surface of the semiconductor layer 2.
  • the polysilicon in these regions is not only formed within the gate trench 6, but also covers the upper corners of the gate trench 6 and is also formed in the mesa region (upper surface of the semiconductor layer 2).
  • the radius of curvature Re of the upper corners of the gate trench 6 is large, which can suppress the concentration of the electric field. This prevents the gate insulating film 7 from being destroyed.
  • the outermost end of the active region 20 shown in FIG. 24 (the portion corresponding to region 109) can electrically connect multiple gate electrodes 8 arranged in a stripe pattern via gate contacts 34, thereby reducing the gate resistance of the gate trenches 6 formed to extend thinly.
  • FIG. 25 is a plan view showing an example of a structure in which an interlayer insulating film 13 is formed and a source contact 31 and a gate contact 34 are formed after the process shown in FIG. 24.
  • gate contacts 34 are formed on the upper surface of gate electrode 8 in regions 108 and 109.
  • a gate electrode 8 is formed in the region 108, and is connected to the gate bonding pad 58 via the gate wiring 18.
  • aluminum is patterned to form a metal wiring 122 (gate wiring 18), and the metal wiring 122 extends to the upper surface of the gate electrode 8 formed in the termination region 30.
  • the metal wiring 122 is then electrically connected to the gate electrode 8 via a contact hole (gate contact 34).
  • the gate wiring 18 in the termination region 30 extends to just below the gate bonding pad 58, and is electrically connected to the gate electrode 8 via the gate contact 34 in the gate bonding pad 58.
  • the gate electrode 8 in the gate trench 6 in the cell array is electrically connected to the gate bonding pad 58 via the gate contact 34 in the center of the active region 20.
  • the gate electrode 8 in the gate trench 6 in the cell array is also electrically connected to other gate wiring 18 in the active region 20 via the gate contact 34 and aluminum layer (electrode portion 121) formed at the end of the active region 20. This reduces the resistance of the gate wiring 18 in the gate trench 6 in the active region 20, resulting in good electrical characteristics (switching characteristics, on-characteristics).
  • the radius of curvature Re of the upper corner of the gate trench 6 in region 108 at the center of the active region 20 where the gate contact 34 is formed, and the radius of curvature Re of the upper corner of the gate trench 6 in region 109 at the end of the active region 20 are made large. Therefore, even when a gate voltage is applied during device operation, the concentration of the electric field at the upper corner of the gate trench 6 can be suppressed, and the destruction of the gate insulating film 7 can be suppressed.
  • ⁇ Configuration of Semiconductor Device> 26 to 30 are cross-sectional views each showing a schematic example of a configuration of a semiconductor device 103 according to this embodiment. As shown in the examples of FIG. 26 to 30, the semiconductor device 103 includes an active region 20 and a termination region 30.
  • the active region 20 there are formed a plurality of gate trenches 6 arranged in a plan view, a gate electrode 8 formed in the gate trench 6, and a gate wiring 18 connected to the gate electrode 8 via a gate contact 34.
  • the gate contact 34 is formed directly below the gate wiring 18 and in the upper layer of the gate electrode 8.
  • the gate electrode 8 is connected to a gate bonding pad 58 located on the periphery of the chip.
  • the gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum, and are formed in the same process.
  • a source electrode 11 is formed on the upper surface of the source region 5 formed on the surface layer of the semiconductor layer 2.
  • the source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31).
  • the source electrode 11 also extends to the source bonding pad 59.
  • a termination trench 16 and a gate electrode 8 are formed in a portion of the termination trench 16.
  • a metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34.
  • the metal wiring 122 is formed in the same process as the gate electrode 8 and the source electrode 11. Since the metal wiring 122 and the gate electrode 8 are formed in parallel connection, the gate resistance can be reduced.
  • the semiconductor device 103 is configured as described above.
  • the structure shown in Figure 26 corresponds to the structure at the stage when the steps from Figure 7 to Figure 9 are completed.
  • a p-type diffusion protection layer 39 is formed by ion implantation of Al into the bottom of the gate trench 6 and the bottom of the gate trench 26.
  • a p-type termination protection layer 49 is formed by ion implantation of Al into the bottom of the termination trench 16.
  • the impurity concentration of Al to be ion-implanted is, for example, 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less, and the depth of ion implantation is preferably, for example, 0.1 ⁇ m or more and 2.0 ⁇ m or less.
  • a resist mask 51 is formed on the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30. Then, Al ions are additionally implanted into the exposed p-type diffusion protection layer 39 and the termination protection layer 49.
  • the impurity concentration of Al is, for example, 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less, and the ion implantation depth is, for example, 0.1 ⁇ m or more and 2.0 ⁇ m or less.
  • the impurity concentration of the diffusion protection layer 39 in the gate trench 6 and gate trench 26 at the boundary between the active region 20 and the termination region 30 becomes lower than the impurity concentration of the diffusion protection layer 9 in the gate trench 6 (a trench formed in a location other than the boundary) where two ion implantations have been performed.
  • the impurity concentration of the diffusion protection layer 39 becomes lower than the impurity concentration of the termination protection layer 19 in the termination trench 16 where two ion implantations have been performed.
  • the annealing process is performed in an inert gas atmosphere such as argon (Ar) or in a vacuum, for example, at a temperature in the range of 1300°C or higher and 1900°C or lower, for example, for 30 seconds or more and 1 hour or less.
  • Ar argon
  • a vacuum for example, at a temperature in the range of 1300°C or higher and 1900°C or lower, for example, for 30 seconds or more and 1 hour or less.
  • a gate insulating film 97 is deposited. Then, a resist mask 52 is formed on the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30, and the gate insulating film 97 in the area not covered by the resist mask 52 is removed by a wet process using hydrofluoric acid or the like.
  • the thickness of the gate insulating film 97 is, for example, 20 nm or more and 150 nm or less.
  • a gate insulating film is further deposited on the entire surface.
  • the thickness of the gate insulating film formed by the second deposition is, for example, 20 nm or more and 150 nm or less.
  • the gate insulating film 87 in some areas is formed to be thicker than the gate insulating film 7 in other areas.
  • the termination trench 16 in the termination region 30 is processed with wide dimensions, while the gate trench 6 or gate trench 26 in the cell section is formed with the minimum processing line width. Because there is a difference in structure between the two, the thermal history in the wafer process causes the expansion coefficients of the materials to differ. This causes residual stress, which results in differences in the electrical characteristics of the elements and also affects the reliability of the semiconductor device.
  • the thickness of the gate insulating film 87 of the cells in the peripheral portion is increased, or the impurity concentration of the diffusion protection layer 39 is designed to be lower than the impurity concentration of the diffusion protection layer 9 of other cells in other active regions 20, thereby reducing the concentrated electric field applied to the gate insulating film 87 when the gate voltage is applied and the semiconductor device is turned on.
  • destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.
  • the semiconductor device includes a drift layer 3 of a first conductivity type (n type), a base region 4 of a second conductivity type (p type) provided on the surface layer of the drift layer 3, a plurality of n-type source regions 5 provided on the surface layer of the base region 4, at least one trench (e.g., gate trench 6, gate trench 26, termination trench 16) extending from the upper surface of the drift layer 3 through the base region 4 into the drift layer 3, a p-type protective layer (e.g., diffusion protective layer 9, diffusion protective layer 39, termination protective layer 19) provided in the drift layer 3 below the trench, a gate insulating film 7 provided along the inside of the trench including the upper corners of the trench, and a gate electrode 8 surrounded by the gate insulating film 7 and provided at least in the trench.
  • n type first conductivity type
  • p type second conductivity type
  • the semiconductor device further includes a source electrode 11 electrically connected to the source region 5 adjacent to the trench (gate trench 6) in the first region, and a gate wiring 18 provided on the upper surface of the gate electrode 8 provided in the trench (gate trench 6 or termination trench 16) in the second region.
  • the radius of curvature Re of the gate insulating film 7 provided in the upper corner of the trench (gate trench 6 or termination trench 16) in the second region is larger than the radius of curvature Rc of the gate insulating film 7 provided in the upper corner of the trench (gate trench 6) in the first region.
  • the gate wiring 18 is provided on the upper surface of the gate electrode 8 that extends to the upper surface of the source region 5. With such a configuration, destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.
  • the gate wiring 18 is connected to the upper surface of the gate electrode 8 extending to the upper surface of the source region 5 via a plurality of contact holes (gate contacts 34).
  • the thickness of the gate insulating film 7 provided in the trench in the first region is equal to the thickness of the gate insulating film 7 provided in the trench in the second region.
  • a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20, and at least one gate trench 26 is provided in the termination region 30. Furthermore, the gate electrode 8 provided in the gate trench 26 provided in the termination region 30 is not electrically connected to the source electrode 11 and the gate wiring 18. According to this configuration, the potential of the gate electrode 8 in the gate trench 26 is floated, thereby suppressing breakdown of the element.
  • a plurality of trenches are provided.
  • the plurality of gate trenches 6 are arranged in a striped pattern in a plan view.
  • the gate wiring 18 is provided across the upper surface of each of the gate electrodes 8 provided in the plurality of gate trenches 6.
  • a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20, and at least one termination trench 16 is provided in the termination region 30.
  • the formation width of the termination trench 16 provided in the termination region 30 is wider than the formation width of the gate trench 6 (or gate trench 26) provided in the active region 20.
  • a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20 surrounded by the termination region 30 in a plan view. Also, the thickness of the gate insulating film 87 provided in the trenches (gate trench 6 and gate trench 26) at the boundary between the active region 20 and the termination region 30 is thicker than the thickness of the gate insulating film 7 provided in the trenches (gate trench 6, termination trench 16) in the active region 20 and termination region 30 other than the boundary.
  • a plurality of trenches are provided. At least one gate trench 6 is provided in the active region 20 surrounded by the termination region 30 in a plan view. Also, the impurity concentration of the protective layer (diffusion protective layer 39) provided below the gate trench 6 and the gate trench 26 at the boundary between the active region 20 and the termination region 30 is lower than the impurity concentration of the protective layer (diffusion protective layer 9, termination protective layer 19) provided below the trench (gate trench 6, termination trench 16) in the active region 20 and the termination region 30 other than the boundary.
  • a p-type base region 4 is provided on the surface of an n-type drift layer 3.
  • a plurality of n-type source regions 5 are provided on the surface of the base region 4.
  • At least one trench e.g., gate trench 6, gate trench 26, termination trench 16
  • a p-type protective layer e.g., diffusion protective layer 9, diffusion protective layer 39, termination protective layer 19
  • the regions separated in a planar view of the trench are defined as a first region and a second region.
  • the upper corners of the trench are etched.
  • the upper corners of the trench are etched.
  • the upper corners of the trench are etched.
  • a gate insulating film 7 is provided along the inside of the trench including the upper corners of the trench.
  • a gate electrode 8 is provided in the trench surrounded by the gate insulating film 7.
  • a source electrode 11 is provided so as to be electrically connected to the source region 5 adjacent to the trench (gate trench 6) in the first region.
  • a gate wiring 18 is provided on the upper surface of the gate electrode 8 provided in the trench (gate trench 6 or termination trench 16) in the second region.
  • the radius of curvature Re of the gate insulating film 7 provided in the upper corner of the trench (gate trench 6 or termination trench 16) in the second region is larger than the radius of curvature Rc of the gate insulating film 7 provided in the upper corner of the trench (gate trench 6) in the first region.
  • drift layer 4 base region, 5 source region, 6 gate trench, 7 gate insulating film, 8 gate electrode, 11 source electrode, 16 termination trench, 18 gate wiring, 20 active region, 26 gate trench, 30 termination region, 34 gate contact, 87 gate insulating film, 97 gate insulating film, 100 semiconductor device, 101 semiconductor device, 102 semiconductor device, 103 semiconductor device, 108 region, 109 region, 1000 region.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2023/000592 2023-01-12 2023-01-12 半導体装置、および、半導体装置の製造方法 Ceased WO2024150368A1 (ja)

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JP2024569941A JP7851428B2 (ja) 2023-01-12 2023-01-12 半導体装置、および、半導体装置の製造方法
DE112023005602.1T DE112023005602T5 (de) 2023-01-12 2023-01-12 Halbleitereinrichtung und Verfahren zum Herstellen einer Halbleitereinrichtung
CN202380089855.3A CN120457788A (zh) 2023-01-12 2023-01-12 半导体装置以及半导体装置的制造方法

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CN121548078A (zh) * 2026-01-19 2026-02-17 广东芯粤能半导体有限公司 集成鳍式结构的元胞结构及其制备方法、SiC功率器件

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JP2007088010A (ja) * 2005-09-20 2007-04-05 Denso Corp 半導体装置およびその製造方法
WO2013076890A1 (ja) * 2011-11-21 2013-05-30 パナソニック株式会社 半導体装置及びその製造方法
JP2013214658A (ja) * 2012-04-03 2013-10-17 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2018060924A (ja) * 2016-10-05 2018-04-12 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2020031157A (ja) * 2018-08-23 2020-02-27 富士電機株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
JP2021082710A (ja) * 2019-11-19 2021-05-27 株式会社デンソー 半導体装置の製造方法
JP2021136313A (ja) * 2020-02-26 2021-09-13 株式会社日立製作所 半導体装置およびその製造方法

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Publication number Priority date Publication date Assignee Title
JP2007088010A (ja) * 2005-09-20 2007-04-05 Denso Corp 半導体装置およびその製造方法
WO2013076890A1 (ja) * 2011-11-21 2013-05-30 パナソニック株式会社 半導体装置及びその製造方法
JP2013214658A (ja) * 2012-04-03 2013-10-17 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2018060924A (ja) * 2016-10-05 2018-04-12 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2020031157A (ja) * 2018-08-23 2020-02-27 富士電機株式会社 炭化珪素半導体装置の製造方法および炭化珪素半導体装置
JP2021082710A (ja) * 2019-11-19 2021-05-27 株式会社デンソー 半導体装置の製造方法
JP2021136313A (ja) * 2020-02-26 2021-09-13 株式会社日立製作所 半導体装置およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN121548078A (zh) * 2026-01-19 2026-02-17 广东芯粤能半导体有限公司 集成鳍式结构的元胞结构及其制备方法、SiC功率器件

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