DE112014007334B3 - Sauerstoffpräzipitation in stark dotierten Siliciumwafern, geschnitten aus nach dem Czochralski-Verfahren gezüchteten Ingots - Google Patents

Sauerstoffpräzipitation in stark dotierten Siliciumwafern, geschnitten aus nach dem Czochralski-Verfahren gezüchteten Ingots Download PDF

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DE112014007334B3
DE112014007334B3 DE112014007334.2T DE112014007334T DE112014007334B3 DE 112014007334 B3 DE112014007334 B3 DE 112014007334B3 DE 112014007334 T DE112014007334 T DE 112014007334T DE 112014007334 B3 DE112014007334 B3 DE 112014007334B3
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concentration
wafer
single crystal
silicon
precipitates
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Robert J. Falster
Vladimir V. Voronkov
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GlobalWafers Co Ltd
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GlobalWafers Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE112014007334.2T 2013-06-11 2014-05-23 Sauerstoffpräzipitation in stark dotierten Siliciumwafern, geschnitten aus nach dem Czochralski-Verfahren gezüchteten Ingots Active DE112014007334B3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/914,925 US9634098B2 (en) 2013-06-11 2013-06-11 Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method
US13/914,925 2013-06-11

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DE112014007334B3 true DE112014007334B3 (de) 2023-08-24

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DE112014007334.2T Active DE112014007334B3 (de) 2013-06-11 2014-05-23 Sauerstoffpräzipitation in stark dotierten Siliciumwafern, geschnitten aus nach dem Czochralski-Verfahren gezüchteten Ingots
DE112014002781.2T Active DE112014002781B9 (de) 2013-06-11 2014-05-23 Verfahren zur Kontrolle der Sauerstoffpräzipitation in stark dotierten Siliciumwafern, geschnitten aus nach dem Czochralski-Verfahren gezüchteten Ingots, und Silicumwafer

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US (1) US9634098B2 (enExample)
JP (1) JP6289621B2 (enExample)
KR (3) KR102071304B1 (enExample)
DE (2) DE112014007334B3 (enExample)
WO (1) WO2014200686A1 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9945048B2 (en) * 2012-06-15 2018-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method
US20150243494A1 (en) * 2014-02-25 2015-08-27 Texas Instruments Incorporated Mechanically robust silicon substrate having group iiia-n epitaxial layer thereon
KR101680213B1 (ko) * 2015-04-06 2016-11-28 주식회사 엘지실트론 실리콘 단결정 잉곳의 성장 방법
KR101759876B1 (ko) * 2015-07-01 2017-07-31 주식회사 엘지실트론 웨이퍼 및 웨이퍼 결함 분석 방법
JP6610056B2 (ja) * 2015-07-28 2019-11-27 株式会社Ｓｕｍｃｏ エピタキシャルシリコンウェーハの製造方法
KR101674819B1 (ko) * 2015-08-12 2016-11-09 주식회사 엘지실트론 단결정 성장 방법
JP6447439B2 (ja) * 2015-09-28 2019-01-09 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
WO2017058928A1 (en) 2015-10-01 2017-04-06 Sunedison Semiconductor Limited Epitaxial growth of defect-free, wafer-scale single-layer graphene on thin films of cobalt
JP6579046B2 (ja) * 2016-06-17 2019-09-25 株式会社Sumco シリコン単結晶の製造方法
EP3653761B1 (en) * 2016-12-28 2024-02-28 Sunedison Semiconductor Limited Silicon wafers with intrinsic gettering and gate oxide integrity yield
JP7306536B1 (ja) 2022-06-14 2023-07-11 信越半導体株式会社 エピタキシャルウェーハの製造方法
CN118507557A (zh) * 2023-09-27 2024-08-16 隆基绿能科技股份有限公司 一种混合掺杂的硅片

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080038526A1 (en) 2004-07-22 2008-02-14 Shin-Etsu Handotai Co., Ltd. Silicon Epitaxial Wafer And Manufacturing Method Thereof
US20090017291A1 (en) 2004-08-31 2009-01-15 Shinsuke Sadamitsu Silicon epitaxial wafer and production method for same
US20130102129A1 (en) 2011-06-03 2013-04-25 Memc Singapore Pte. Ltd. (Uen200614794D) Processes for suppressing minority carrier lifetime degradation in silicon wafers

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3204159A (en) 1960-09-14 1965-08-31 Bramley Jenny Rectifying majority carrier device
JPS543479A (en) 1977-06-09 1979-01-11 Toshiba Corp Semiconductor device and its manufacture
JP2617798B2 (ja) 1989-09-22 1997-06-04 三菱電機株式会社 積層型半導体装置およびその製造方法
US5024723A (en) 1990-05-07 1991-06-18 Goesele Ulrich M Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning
JP2726583B2 (ja) * 1991-11-18 1998-03-11 三菱マテリアルシリコン株式会社 半導体基板
JPH07106512A (ja) 1993-10-04 1995-04-21 Sharp Corp 分子イオン注入を用いたｓｉｍｏｘ処理方法
WO1998005063A1 (en) 1996-07-29 1998-02-05 Sumitomo Sitix Corporation Silicon epitaxial wafer and method for manufacturing the same
US6503594B2 (en) * 1997-02-13 2003-01-07 Samsung Electronics Co., Ltd. Silicon wafers having controlled distribution of defects and slip
JPH10270455A (ja) * 1997-03-26 1998-10-09 Toshiba Corp 半導体基板の製造方法
US6190631B1 (en) 1997-04-09 2001-02-20 Memc Electronic Materials, Inc. Low defect density, ideal oxygen precipitating silicon
DE69813041T2 (de) 1997-04-09 2004-01-15 Memc Electronic Materials Freistellenbeherrschendes Silizium mit niedriger Fehlerdichte
US5919303A (en) 1997-10-16 1999-07-06 Memc Electronic Materials, Inc. Process for preparing a silicon melt from a polysilicon charge
US5935328A (en) 1997-11-25 1999-08-10 Memc Electronic Materials, Inc. Apparatus for use in crystal pulling
JP4085467B2 (ja) * 1998-04-21 2008-05-14 株式会社Ｓｕｍｃｏ シリコンウェーハとシリコンエピタキシャルウェーハ並びにその製造方法
US6089285A (en) 1998-04-29 2000-07-18 Memc Electronics Materials, Inc. Method and system for supplying semiconductor source material
JP4634553B2 (ja) * 1999-06-08 2011-02-16 シルトロニック・ジャパン株式会社 シリコン単結晶ウエーハおよびその製造方法
JP3687456B2 (ja) * 2000-01-05 2005-08-24 三菱住友シリコン株式会社 シリコンウェーハにｉｇ効果を付与する熱処理方法及びこの方法によりｉｇ効果が付与されたｉｇウェーハ
JP4131077B2 (ja) 2000-06-30 2008-08-13 株式会社Ｓｕｍｃｏ シリコンウェーハの製造方法
US6547875B1 (en) * 2000-09-25 2003-04-15 Mitsubishi Materials Silicon Corporation Epitaxial wafer and a method for manufacturing the same
US6894366B2 (en) * 2000-10-10 2005-05-17 Texas Instruments Incorporated Bipolar junction transistor with a counterdoped collector region
KR100389250B1 (ko) * 2000-11-25 2003-06-25 미쯔비시 마테리알 실리콘 가부시끼가이샤 실리콘 웨이퍼 및 그 제조 방법
JP4862221B2 (ja) 2001-04-03 2012-01-25 信越半導体株式会社 ｎ型シリコン単結晶ウェーハ及びその製造方法
US6663709B2 (en) 2001-06-26 2003-12-16 Memc Electronic Materials, Inc. Crystal puller and method for growing monocrystalline silicon ingots
JP2003124219A (ja) 2001-10-10 2003-04-25 Sumitomo Mitsubishi Silicon Corp シリコンウエーハおよびエピタキシャルシリコンウエーハ
US6905771B2 (en) 2002-11-11 2005-06-14 Sumitomo Mitsubishi Silicon Corporation Silicon wafer
JP2005333090A (ja) 2004-05-21 2005-12-02 Sumco Corp Ｐ型シリコンウェーハおよびその熱処理方法
JP4655557B2 (ja) * 2004-09-10 2011-03-23 信越半導体株式会社 Ｓｏｉ基板の製造方法及びｓｏｉ基板
US7485928B2 (en) 2005-11-09 2009-02-03 Memc Electronic Materials, Inc. Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
JP2007220825A (ja) 2006-02-15 2007-08-30 Sumco Corp シリコンウェーハの製造方法
US20090004426A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
TW200937530A (en) 2007-12-11 2009-09-01 Sumco Corp Silicon substrate and manufacturing method thereof
JP2010283144A (ja) * 2009-06-04 2010-12-16 Sumco Corp シリコンウェーハ及びその製造方法、並びに、半導体デバイスの製造方法
JP2010283295A (ja) * 2009-06-08 2010-12-16 Sumco Corp 半導体デバイスの製造方法及びシリコンウェーハの処理装置
JP2011253978A (ja) 2010-06-03 2011-12-15 Sumco Corp エピタキシャル基板およびその製造方法
JP5572569B2 (ja) * 2011-02-24 2014-08-13 信越半導体株式会社 シリコン基板の製造方法及びシリコン基板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080038526A1 (en) 2004-07-22 2008-02-14 Shin-Etsu Handotai Co., Ltd. Silicon Epitaxial Wafer And Manufacturing Method Thereof
US20090017291A1 (en) 2004-08-31 2009-01-15 Shinsuke Sadamitsu Silicon epitaxial wafer and production method for same
US20130102129A1 (en) 2011-06-03 2013-04-25 Memc Singapore Pte. Ltd. (Uen200614794D) Processes for suppressing minority carrier lifetime degradation in silicon wafers

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LI, C. [et al.]: Effect of Rapid Thermal Process on Oxygen. In: Japanese Journal of Applied Physics, Vol. 42, 2003, S. 7290 - 7291.
SHIMIZU, Y. [et al.]: Impact of carbon coimplantation on boron behavior in silicon: Carbon-boron coclustering and suppression of boron diffusion. In: Appl. Phys. Lett., Vol. 98, 2011, Seiten 232101-1 – 232101-3.

Also Published As

Publication number Publication date
JP2016526783A (ja) 2016-09-05
DE112014002781T5 (de) 2016-03-10
KR20200044152A (ko) 2020-04-28
KR102172905B1 (ko) 2020-11-03
KR102071304B1 (ko) 2020-01-31
US9634098B2 (en) 2017-04-25
WO2014200686A1 (en) 2014-12-18
US20140361408A1 (en) 2014-12-11
DE112014002781B9 (de) 2021-07-29
KR20160019495A (ko) 2016-02-19
DE112014002781B4 (de) 2020-06-18
KR20200011563A (ko) 2020-02-03
KR102172904B1 (ko) 2020-11-03
JP6289621B2 (ja) 2018-03-07

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