DE102014017099A1 - Abdeckungsverbesserung und energiebewusstes Taktsystem für einen strukturellen Delay-Fault-Test - Google Patents

Abdeckungsverbesserung und energiebewusstes Taktsystem für einen strukturellen Delay-Fault-Test Download PDF

Info

Publication number
DE102014017099A1
DE102014017099A1 DE102014017099.3A DE102014017099A DE102014017099A1 DE 102014017099 A1 DE102014017099 A1 DE 102014017099A1 DE 102014017099 A DE102014017099 A DE 102014017099A DE 102014017099 A1 DE102014017099 A1 DE 102014017099A1
Authority
DE
Germany
Prior art keywords
clock
test
scan
clock gating
gating cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102014017099.3A
Other languages
German (de)
English (en)
Inventor
Zhen Song Li
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE102014017099A1 publication Critical patent/DE102014017099A1/de
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
DE102014017099.3A 2013-11-19 2014-11-19 Abdeckungsverbesserung und energiebewusstes Taktsystem für einen strukturellen Delay-Fault-Test Withdrawn DE102014017099A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/083,624 2013-11-19
US14/083,624 US9377511B2 (en) 2013-11-19 2013-11-19 Coverage enhancement and power aware clock system for structural delay-fault test

Publications (1)

Publication Number Publication Date
DE102014017099A1 true DE102014017099A1 (de) 2015-05-21

Family

ID=53174545

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102014017099.3A Withdrawn DE102014017099A1 (de) 2013-11-19 2014-11-19 Abdeckungsverbesserung und energiebewusstes Taktsystem für einen strukturellen Delay-Fault-Test

Country Status (4)

Country Link
US (1) US9377511B2 (https=)
JP (1) JP2015099146A (https=)
KR (1) KR101690376B1 (https=)
DE (1) DE102014017099A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10447461B2 (en) * 2015-12-01 2019-10-15 Infineon Technologies Austria Ag Accessing data via different clocks
CN106992770B (zh) * 2016-01-21 2021-03-30 华为技术有限公司 时钟电路及其传输时钟信号的方法
KR102630258B1 (ko) * 2021-10-26 2024-01-25 연세대학교 산학협력단 로직 비스트 캡쳐 전력 감소 회로 및 방법
US12210058B1 (en) * 2022-07-29 2025-01-28 Marvell Asia Pte Ltd Clock gating for power reduction during testing
US12517544B2 (en) 2023-06-20 2026-01-06 Stmicroelectronics International N.V. Power reduction and effective timing exceptions handling in at-speed capture

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8091002B2 (en) * 2001-02-15 2012-01-03 Syntest Technologies, Inc. Multiple-capture DFT system to reduce peak capture power during self-test or scan test
JP4627118B2 (ja) 2001-04-26 2011-02-09 ルネサスエレクトロニクス株式会社 スキャンテスト用回路
US6880137B1 (en) * 2001-08-03 2005-04-12 Inovys Dynamically reconfigurable precision signal delay test system for automatic test equipment
JP2005032102A (ja) * 2003-07-09 2005-02-03 Matsushita Electric Ind Co Ltd スキャンテスト設計方法、スキャンテスト回路、スキャンフリップフロップ回路、スキャンテスト回路挿入用ｃａｄプログラム、大規模集積回路及び携帯デジタル機器
US6972592B2 (en) * 2003-11-24 2005-12-06 Lsi Logic Corporation Self-timed scan circuit for ASIC fault testing
DE602004023888D1 (de) * 2004-12-13 2009-12-10 Infineon Technologies Ag Schaltung und verfahren für bei geschwindigkeit durchgeführten scan-test
US7613971B2 (en) * 2005-02-08 2009-11-03 Nec Electronics Corporation Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit
TW200801550A (en) * 2006-01-06 2008-01-01 Koninkl Philips Electronics Nv IC testing methods and apparatus
US20080282122A1 (en) * 2007-05-09 2008-11-13 Amar Guettaf Single scan clock in a multi-clock domain
US20100138709A1 (en) * 2008-10-22 2010-06-03 Laung-Terng Wang Method and apparatus for delay fault coverage enhancement
JP5275136B2 (ja) 2009-05-28 2013-08-28 ルネサスエレクトロニクス株式会社 半導体集積回路
US8028209B2 (en) * 2009-06-26 2011-09-27 Intel Corporation Scalable scan system for system-on-chip design
US8464117B2 (en) * 2010-05-25 2013-06-11 Freescale Semiconductor, Inc. System for testing integrated circuit with asynchronous clock domains
US9075110B2 (en) * 2010-10-05 2015-07-07 Kyushu Institute Of Technology Fault detection system, acquisition apparatus, fault detection method, program, and non-transitory computer-readable medium
US8862955B2 (en) * 2010-12-29 2014-10-14 Stmicroelectronics S.R.L. Apparatus for at-speed testing, in inter-domain mode, of a multi-clock-domain digital integrated circuit according to BIST or SCAN techniques
JP2013156073A (ja) 2012-01-27 2013-08-15 Renesas Electronics Corp 半導体装置
JP2013224917A (ja) * 2012-03-22 2013-10-31 Renesas Electronics Corp スキャンテスト回路、テストパタン生成制御回路及びスキャンテスト制御方法

Also Published As

Publication number Publication date
JP2015099146A (ja) 2015-05-28
US9377511B2 (en) 2016-06-28
KR101690376B1 (ko) 2016-12-27
KR20150058060A (ko) 2015-05-28
US20150143189A1 (en) 2015-05-21

Similar Documents

Publication Publication Date Title
DE60225898T2 (de) Mehrfacherfassungs-dft-system zum detektieren oder auffinden von überschreitenden taktbereichsfehlern während der selbstprüfung oder scan-prüfung
DE60211659T2 (de) Verfahren und vorrichtung zur diagnose von ausfällen in einer integrierten schaltung unter verwendung von techniken des typs design-for-debug (dfd)
DE69126575T2 (de) Durch Ereignis befähigte Prüfarchitektur
DE69107463T2 (de) Integrierte Schaltung, System und Verfahren zur Fehlererzeugung.
DE2349324A1 (de) Verfahren und vorrichtung zum pruefen funktioneller logischer schaltungen
DE68925813T2 (de) Verfahren und vorrichtung zum nachweis von fehlern in halbleiterschaltungen
DE102014017099A1 (de) Abdeckungsverbesserung und energiebewusstes Taktsystem für einen strukturellen Delay-Fault-Test
DE102016116717A1 (de) Scan-Ketten-Schaltung, die eine Injektion eines logischen Selbsttestmusters während der Laufzeit unterstützt
DE69126848T2 (de) Integrierte Halbleiterschaltung
DE69220709T2 (de) Prüfmustererzeugungseinrichtung für sequentielle Logikschaltung einer integrierten Schaltung und Verfahren dazu
DE10053878A1 (de) Halbleiterprüfsystem
DE10118141A1 (de) Anwendungsspezifisches ereignisgestütztes Halbleiter-Speicherprüfsystem
DE69021683T2 (de) Selbstprüfbare Randlogikschaltung.
DE69217524T2 (de) Testschaltung, vorgesehen in digitalen logischen Schaltungen
DE69017169T2 (de) Testen integrierter Schaltungen unter Verwendung von Taktgeberstössen.
DE10339940A1 (de) System und Verfahren zum heterogenen Mehrstellentesten
DE69516303T2 (de) Prüfverfahren und vorrichtung für pegelempfindliche abfragekonstruktionen
DE112019004358T5 (de) Verfahren zur takt-gate-analyse von entwürfen für elektronische systeme und zugehörige systeme, verfahren und vorrichtungen
DE102009025412A1 (de) Integrierte Schaltung und Verfahren zum Schützen eines Schaltungsteils einer integrierten Schaltung, der geschützt werden soll
DE69433542T2 (de) Prüfung, sequenziellogischer Schaltung auf grund einer kombinatorischen Logikschaltungsveränderung
DE102006024507B4 (de) Integrierte Schaltung und Verfahren zum Erkennen von Laufzeitfehlern in integrierten Schaltungen
DE2902375A1 (de) Logikbaustein fuer integrierte digitalschaltungen
DE69026809T2 (de) Verfahren zur Treibersteuerung integrierter Schaltungen während der Prüfung
DE69533018T2 (de) Struktur und Leistungsabtastprüfung
EP1430320B1 (de) Elektronischer baustein und verfahren zu dessen qualifizierungsmessung

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R083 Amendment of/additions to inventor(s)
R082 Change of representative

Representative=s name: VIERING, JENTSCHURA & PARTNER MBB PATENT- UND , DE

R016 Response to examination communication
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee