DE102006036963A1 - Halbleiterbauelement mit Kontaktstelle und Herstellungsverfahren - Google Patents

Halbleiterbauelement mit Kontaktstelle und Herstellungsverfahren Download PDF

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Publication number
DE102006036963A1
DE102006036963A1 DE102006036963A DE102006036963A DE102006036963A1 DE 102006036963 A1 DE102006036963 A1 DE 102006036963A1 DE 102006036963 A DE102006036963 A DE 102006036963A DE 102006036963 A DE102006036963 A DE 102006036963A DE 102006036963 A1 DE102006036963 A1 DE 102006036963A1
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Germany
Prior art keywords
ferrite
layer
further characterized
forming
signal line
Prior art date
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Ceased
Application number
DE102006036963A
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German (de)
English (en)
Inventor
Eun-Seok Song
Un-Byoung Hwaseong Kang
Si-Hoon Yongin Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Filing date
Publication date
Priority claimed from KR1020050070396A external-priority patent/KR100606654B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102006036963A1 publication Critical patent/DE102006036963A1/de
Ceased legal-status Critical Current

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    • HELECTRICITY
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE102006036963A 2005-08-01 2006-08-01 Halbleiterbauelement mit Kontaktstelle und Herstellungsverfahren Ceased DE102006036963A1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020050070396A KR100606654B1 (ko) 2005-08-01 2005-08-01 전자파 장해 저감용 페라이트 차폐 구조를 구비하는 반도체패키지 및 그 제조 방법
KR10-2005-0070396 2005-08-01
US11/387,848 2006-03-24
US11/387,848 US7495317B2 (en) 2005-08-01 2006-03-24 Semiconductor package with ferrite shielding structure

Publications (1)

Publication Number Publication Date
DE102006036963A1 true DE102006036963A1 (de) 2007-02-15

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DE102006036963A Ceased DE102006036963A1 (de) 2005-08-01 2006-08-01 Halbleiterbauelement mit Kontaktstelle und Herstellungsverfahren

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JP (1) JP5138181B2 (ja)
DE (1) DE102006036963A1 (ja)

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Publication number Priority date Publication date Assignee Title
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
KR101374148B1 (ko) * 2012-06-08 2014-03-17 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
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